258 lines
9.6 KiB
C
258 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2015-2021 Texas Instruments Incorporated - https://www.ti.com
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*/
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#ifndef __ICSS_SWITCH_H
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#define __ICSS_SWITCH_H
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/* Basic Switch Parameters
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* Used to auto compute offset addresses on L3 OCMC RAM. Do not modify these
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* without changing firmware accordingly
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*/
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#define SWITCH_BUFFER_SIZE (64 * 1024) /* L3 buffer */
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#define ICSS_BLOCK_SIZE 32 /* data bytes per BD */
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#define BD_SIZE 4 /* byte buffer descriptor */
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#define NUM_QUEUES 4 /* Queues on Port 0/1/2 */
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#define PORT_LINK_MASK 0x1
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#define PORT_IS_HD_MASK 0x2
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/* Physical Port queue size (number of BDs). Same for both ports */
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#define QUEUE_1_SIZE 97 /* Network Management high */
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#define QUEUE_2_SIZE 97 /* Network Management low */
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#define QUEUE_3_SIZE 97 /* Protocol specific */
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#define QUEUE_4_SIZE 97 /* NRT (IP,ARP, ICMP) */
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/* Host queue size (number of BDs). Each BD points to data buffer of 32 bytes.
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* HOST PORT QUEUES can buffer up to 4 full sized frames per queue
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*/
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#define HOST_QUEUE_1_SIZE 194 /* Protocol and VLAN priority 7 & 6 */
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#define HOST_QUEUE_2_SIZE 194 /* Protocol mid */
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#define HOST_QUEUE_3_SIZE 194 /* Protocol low */
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#define HOST_QUEUE_4_SIZE 194 /* NRT (IP, ARP, ICMP) */
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#define COL_QUEUE_SIZE 0
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/* NRT Buffer descriptor definition
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* Each buffer descriptor points to a max 32 byte block and has 32 bit in size
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* to have atomic operation.
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* PRU can address bytewise into memory.
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* Definition of 32 bit descriptor is as follows
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*
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* Bits Name Meaning
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* =============================================================================
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* 0..7 Index points to index in buffer queue, max 256 x 32
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* byte blocks can be addressed
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* 6 LookupSuccess For switch, FDB lookup was successful (source
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* MAC address found in FDB).
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* For RED, NodeTable lookup was successful.
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* 7 Flood Packet should be flooded (destination MAC
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* address found in FDB). For switch only.
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* 8..12 Block_length number of valid bytes in this specific block.
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* Will be <=32 bytes on last block of packet
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* 13 More "More" bit indicating that there are more blocks
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* 14 Shadow indicates that "index" is pointing into shadow
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* buffer
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* 15 TimeStamp indicates that this packet has time stamp in
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* separate buffer - only needed if PTP runs on
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* host
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* 16..17 Port different meaning for ingress and egress,
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* Ingress: Port = 0 indicates phy port 1 and
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* Port = 1 indicates phy port 2.
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* Egress: 0 sends on phy port 1 and 1 sends on
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* phy port 2. Port = 2 goes over MAC table
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* look-up
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* 18..28 Length 11 bit of total packet length which is put into
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* first BD only so that host access only one BD
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* 29 VlanTag indicates that packet has Length/Type field of
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* 0x08100 with VLAN tag in following byte
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* 30 Broadcast indicates that packet goes out on both physical
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* ports, there will be two bd but only one buffer
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* 31 Error indicates there was an error in the packet
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*/
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#define PRUETH_BD_START_FLAG_MASK BIT(0)
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#define PRUETH_BD_START_FLAG_SHIFT 0
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#define PRUETH_BD_HSR_FRAME_MASK BIT(4)
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#define PRUETH_BD_HSR_FRAME_SHIFT 4
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#define PRUETH_BD_SUP_HSR_FRAME_MASK BIT(5)
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#define PRUETH_BD_SUP_HSR_FRAME_SHIFT 5
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#define PRUETH_BD_LOOKUP_SUCCESS_MASK BIT(6)
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#define PRUETH_BD_LOOKUP_SUCCESS_SHIFT 6
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#define PRUETH_BD_SW_FLOOD_MASK BIT(7)
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#define PRUETH_BD_SW_FLOOD_SHIFT 7
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#define PRUETH_BD_SHADOW_MASK BIT(14)
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#define PRUETH_BD_SHADOW_SHIFT 14
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#define PRUETH_BD_TIMESTAMP_MASK BIT(15)
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#define PRUETH_BD_TIMESTAMP_SHIFT 15
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#define PRUETH_BD_PORT_MASK GENMASK(17, 16)
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#define PRUETH_BD_PORT_SHIFT 16
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#define PRUETH_BD_LENGTH_MASK GENMASK(28, 18)
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#define PRUETH_BD_LENGTH_SHIFT 18
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#define PRUETH_BD_BROADCAST_MASK BIT(30)
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#define PRUETH_BD_BROADCAST_SHIFT 30
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#define PRUETH_BD_ERROR_MASK BIT(31)
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#define PRUETH_BD_ERROR_SHIFT 31
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/* The following offsets indicate which sections of the memory are used
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* for EMAC internal tasks
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*/
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#define DRAM_START_OFFSET 0x1E98
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#define SRAM_START_OFFSET 0x400
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/* General Purpose Statistics
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* These are present on both PRU0 and PRU1 DRAM
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*/
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/* base statistics offset */
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#define STATISTICS_OFFSET 0x1F00
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#define STAT_SIZE 0x98
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/* Offset for storing
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* 1. Storm Prevention Params
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* 2. PHY Speed Offset
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* 3. Port Status Offset
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* These are present on both PRU0 and PRU1
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*/
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/* 4 bytes */
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#define STORM_PREVENTION_OFFSET_BC (STATISTICS_OFFSET + STAT_SIZE)
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/* 4 bytes */
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#define PHY_SPEED_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 4)
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/* 1 byte */
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#define PORT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 8)
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/* 1 byte */
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#define COLLISION_COUNTER (STATISTICS_OFFSET + STAT_SIZE + 9)
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/* 4 bytes */
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#define RX_PKT_SIZE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 10)
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/* 4 bytes */
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#define PORT_CONTROL_ADDR (STATISTICS_OFFSET + STAT_SIZE + 14)
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/* 6 bytes */
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#define PORT_MAC_ADDR (STATISTICS_OFFSET + STAT_SIZE + 18)
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/* 1 byte */
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#define RX_INT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 24)
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/* 4 bytes */
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#define STORM_PREVENTION_OFFSET_MC (STATISTICS_OFFSET + STAT_SIZE + 25)
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/* 4 bytes */
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#define STORM_PREVENTION_OFFSET_UC (STATISTICS_OFFSET + STAT_SIZE + 29)
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/* 4 bytes ? */
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#define STP_INVALID_STATE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 33)
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/* DRAM Offsets for EMAC
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* Present on Both DRAM0 and DRAM1
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*/
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/* 4 queue descriptors for port tx = 32 bytes */
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#define TX_CONTEXT_Q1_OFFSET_ADDR (PORT_QUEUE_DESC_OFFSET + 32)
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#define PORT_QUEUE_DESC_OFFSET (ICSS_EMAC_TTS_CYC_TX_SOF + 8)
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/* EMAC Time Triggered Send Offsets */
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#define ICSS_EMAC_TTS_CYC_TX_SOF (ICSS_EMAC_TTS_PREV_TX_SOF + 8)
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#define ICSS_EMAC_TTS_PREV_TX_SOF \
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(ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET + 4)
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#define ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET (ICSS_EMAC_TTS_STATUS_OFFSET \
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+ 4)
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#define ICSS_EMAC_TTS_STATUS_OFFSET (ICSS_EMAC_TTS_CFG_TIME_OFFSET + 4)
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#define ICSS_EMAC_TTS_CFG_TIME_OFFSET (ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET + 4)
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#define ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET \
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(ICSS_EMAC_TTS_CYCLE_START_OFFSET + 8)
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#define ICSS_EMAC_TTS_CYCLE_START_OFFSET ICSS_EMAC_TTS_BASE_OFFSET
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#define ICSS_EMAC_TTS_BASE_OFFSET DRAM_START_OFFSET
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/* Shared RAM offsets for EMAC */
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/* Queue Descriptors */
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/* 4 queue descriptors for port 0 (host receive). 32 bytes */
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#define HOST_QUEUE_DESC_OFFSET (HOST_QUEUE_SIZE_ADDR + 16)
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/* table offset for queue size:
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* 3 ports * 4 Queues * 1 byte offset = 12 bytes
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*/
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#define HOST_QUEUE_SIZE_ADDR (HOST_QUEUE_OFFSET_ADDR + 8)
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/* table offset for queue:
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* 4 Queues * 2 byte offset = 8 bytes
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*/
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#define HOST_QUEUE_OFFSET_ADDR (HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR + 8)
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/* table offset for Host queue descriptors:
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* 1 ports * 4 Queues * 2 byte offset = 8 bytes
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*/
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#define HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR (HOST_Q4_RX_CONTEXT_OFFSET + 8)
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/* Host Port Rx Context */
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#define HOST_Q4_RX_CONTEXT_OFFSET (HOST_Q3_RX_CONTEXT_OFFSET + 8)
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#define HOST_Q3_RX_CONTEXT_OFFSET (HOST_Q2_RX_CONTEXT_OFFSET + 8)
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#define HOST_Q2_RX_CONTEXT_OFFSET (HOST_Q1_RX_CONTEXT_OFFSET + 8)
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#define HOST_Q1_RX_CONTEXT_OFFSET (EMAC_PROMISCUOUS_MODE_OFFSET + 4)
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/* Promiscuous mode control */
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#define EMAC_P1_PROMISCUOUS_BIT BIT(0)
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#define EMAC_P2_PROMISCUOUS_BIT BIT(1)
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#define EMAC_PROMISCUOUS_MODE_OFFSET (EMAC_RESERVED + 4)
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#define EMAC_RESERVED EOF_48K_BUFFER_BD
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/* allow for max 48k buffer which spans the descriptors up to 0x1800 6kB */
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#define EOF_48K_BUFFER_BD (P0_BUFFER_DESC_OFFSET + HOST_BD_SIZE + \
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PORT_BD_SIZE)
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#define HOST_BD_SIZE ((HOST_QUEUE_1_SIZE + \
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HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + \
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HOST_QUEUE_4_SIZE) * BD_SIZE)
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#define PORT_BD_SIZE ((QUEUE_1_SIZE + QUEUE_2_SIZE + \
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QUEUE_3_SIZE + QUEUE_4_SIZE) * 2 * BD_SIZE)
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#define END_OF_BD_POOL (P2_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE)
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#define P2_Q4_BD_OFFSET (P2_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE)
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#define P2_Q3_BD_OFFSET (P2_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE)
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#define P2_Q2_BD_OFFSET (P2_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE)
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#define P2_Q1_BD_OFFSET (P1_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE)
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#define P1_Q4_BD_OFFSET (P1_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE)
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#define P1_Q3_BD_OFFSET (P1_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE)
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#define P1_Q2_BD_OFFSET (P1_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE)
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#define P1_Q1_BD_OFFSET (P0_Q4_BD_OFFSET + HOST_QUEUE_4_SIZE * BD_SIZE)
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#define P0_Q4_BD_OFFSET (P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE)
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#define P0_Q3_BD_OFFSET (P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE)
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#define P0_Q2_BD_OFFSET (P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE)
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#define P0_Q1_BD_OFFSET P0_BUFFER_DESC_OFFSET
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#define P0_BUFFER_DESC_OFFSET SRAM_START_OFFSET
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/* Memory Usage of L3 OCMC RAM */
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/* L3 64KB Memory - mainly buffer Pool */
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#define END_OF_BUFFER_POOL (P2_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P2_Q4_BUFFER_OFFSET (P2_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P2_Q3_BUFFER_OFFSET (P2_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P2_Q2_BUFFER_OFFSET (P2_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P2_Q1_BUFFER_OFFSET (P1_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P1_Q4_BUFFER_OFFSET (P1_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P1_Q3_BUFFER_OFFSET (P1_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P1_Q2_BUFFER_OFFSET (P1_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P1_Q1_BUFFER_OFFSET (P0_Q4_BUFFER_OFFSET + HOST_QUEUE_4_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P0_Q4_BUFFER_OFFSET (P0_Q3_BUFFER_OFFSET + HOST_QUEUE_3_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P0_Q3_BUFFER_OFFSET (P0_Q2_BUFFER_OFFSET + HOST_QUEUE_2_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P0_Q2_BUFFER_OFFSET (P0_Q1_BUFFER_OFFSET + HOST_QUEUE_1_SIZE * \
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ICSS_BLOCK_SIZE)
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#define P0_COL_BUFFER_OFFSET 0xEE00
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#define P0_Q1_BUFFER_OFFSET 0x0000
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#endif /* __ICSS_SWITCH_H */
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