115 lines
4.4 KiB
C
115 lines
4.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
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/* DISP_CC clocks */
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#define DISP_CC_ESYNC0_CLK 0
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#define DISP_CC_ESYNC0_CLK_SRC 1
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#define DISP_CC_ESYNC1_CLK 2
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#define DISP_CC_ESYNC1_CLK_SRC 3
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#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
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#define DISP_CC_MDSS_AHB1_CLK 5
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#define DISP_CC_MDSS_AHB_CLK 6
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#define DISP_CC_MDSS_AHB_CLK_SRC 7
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#define DISP_CC_MDSS_BYTE0_CLK 8
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 9
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 11
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#define DISP_CC_MDSS_BYTE1_CLK 12
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 13
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 15
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 16
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 18
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 20
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#define DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK 21
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#define DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC 22
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 23
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 24
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 25
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 26
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 27
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28
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#define DISP_CC_MDSS_DPTX1_AUX_CLK 29
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#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30
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#define DISP_CC_MDSS_DPTX1_LINK_CLK 31
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#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32
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#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33
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#define DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK 34
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#define DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC 35
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#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40
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#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41
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#define DISP_CC_MDSS_DPTX2_AUX_CLK 42
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#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43
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#define DISP_CC_MDSS_DPTX2_LINK_CLK 44
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#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 45
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#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 46
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#define DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK 47
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#define DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC 48
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#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53
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#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 54
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#define DISP_CC_MDSS_DPTX3_AUX_CLK 55
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#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 56
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#define DISP_CC_MDSS_DPTX3_LINK_CLK 57
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#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58
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#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59
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#define DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK 60
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#define DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC 61
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#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64
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#define DISP_CC_MDSS_ESC0_CLK 65
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#define DISP_CC_MDSS_ESC0_CLK_SRC 66
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#define DISP_CC_MDSS_ESC1_CLK 67
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#define DISP_CC_MDSS_ESC1_CLK_SRC 68
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#define DISP_CC_MDSS_MDP1_CLK 69
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#define DISP_CC_MDSS_MDP_CLK 70
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#define DISP_CC_MDSS_MDP_CLK_SRC 71
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#define DISP_CC_MDSS_MDP_LUT1_CLK 72
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#define DISP_CC_MDSS_MDP_LUT_CLK 73
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 74
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#define DISP_CC_MDSS_PCLK0_CLK 75
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 76
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#define DISP_CC_MDSS_PCLK1_CLK 77
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 78
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#define DISP_CC_MDSS_PCLK2_CLK 79
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#define DISP_CC_MDSS_PCLK2_CLK_SRC 80
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#define DISP_CC_MDSS_RSCC_AHB_CLK 81
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 82
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#define DISP_CC_MDSS_VSYNC1_CLK 83
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#define DISP_CC_MDSS_VSYNC_CLK 84
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 85
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#define DISP_CC_OSC_CLK 86
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#define DISP_CC_OSC_CLK_SRC 87
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#define DISP_CC_PLL0 88
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#define DISP_CC_PLL1 89
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#define DISP_CC_SLEEP_CLK 90
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#define DISP_CC_SLEEP_CLK_SRC 91
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#define DISP_CC_XO_CLK 92
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#define DISP_CC_XO_CLK_SRC 93
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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#endif
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