242 lines
6.2 KiB
C
242 lines
6.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
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#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_NL2 8
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#define SRST_CORE_BIU 9
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#define SRST_CORE_CRYPTO 10
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#define SRST_P_DBG 11
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#define SRST_POT_DBG 12
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#define SRST_NT_DBG 13
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#define SRST_P_CORE_GRF 14
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#define SRST_P_DAPLITE_BIU 15
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#define SRST_P_CPU_BIU 16
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#define SRST_REF_PVTPLL_CORE 17
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#define SRST_A_BUS_VOPGL_BIU 18
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#define SRST_A_BUS_H_BIU 19
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#define SRST_A_SYSMEM_BIU 20
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#define SRST_A_BUS_BIU 21
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#define SRST_H_BUS_BIU 22
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#define SRST_P_BUS_BIU 23
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#define SRST_P_DFT2APB 24
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#define SRST_P_BUS_GRF 25
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#define SRST_A_BUS_M_BIU 26
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#define SRST_A_GIC 27
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#define SRST_A_SPINLOCK 28
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#define SRST_A_DMAC 29
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#define SRST_P_TIMER 30
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#define SRST_TIMER0 31
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#define SRST_TIMER1 32
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#define SRST_TIMER2 33
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#define SRST_TIMER3 34
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#define SRST_TIMER4 35
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#define SRST_TIMER5 36
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#define SRST_P_JDBCK_DAP 37
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#define SRST_JDBCK_DAP 38
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#define SRST_P_WDT_NS 39
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#define SRST_T_WDT_NS 40
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#define SRST_H_TRNG_NS 41
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#define SRST_P_UART0 42
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#define SRST_S_UART0 43
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#define SRST_PKA_CRYPTO 44
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#define SRST_A_CRYPTO 45
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#define SRST_H_CRYPTO 46
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#define SRST_P_DMA2DDR 47
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#define SRST_A_DMA2DDR 48
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#define SRST_P_PWM0 49
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#define SRST_PWM0 50
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#define SRST_P_PWM1 51
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#define SRST_PWM1 52
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#define SRST_P_SCR 53
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#define SRST_A_DCF 54
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#define SRST_P_INTMUX 55
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#define SRST_A_VPU_BIU 56
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#define SRST_H_VPU_BIU 57
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#define SRST_P_VPU_BIU 58
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#define SRST_A_VPU 59
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#define SRST_H_VPU 60
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#define SRST_P_CRU_PCIE 61
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#define SRST_P_VPU_GRF 62
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#define SRST_H_SFC 63
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#define SRST_S_SFC 64
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#define SRST_C_EMMC 65
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#define SRST_H_EMMC 66
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#define SRST_A_EMMC 67
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#define SRST_B_EMMC 68
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#define SRST_T_EMMC 69
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#define SRST_P_GPIO1 70
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#define SRST_DB_GPIO1 71
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#define SRST_A_VPU_L_BIU 72
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#define SRST_P_VPU_IOC 73
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#define SRST_H_SAI_I2S0 74
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#define SRST_M_SAI_I2S0 75
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#define SRST_H_SAI_I2S2 76
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#define SRST_M_SAI_I2S2 77
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#define SRST_P_ACODEC 78
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#define SRST_P_GPIO3 79
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#define SRST_DB_GPIO3 80
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#define SRST_P_SPI1 81
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#define SRST_SPI1 82
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#define SRST_P_UART2 83
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#define SRST_S_UART2 84
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#define SRST_P_UART5 85
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#define SRST_S_UART5 86
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#define SRST_P_UART6 87
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#define SRST_S_UART6 88
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#define SRST_P_UART7 89
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#define SRST_S_UART7 90
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#define SRST_P_I2C3 91
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#define SRST_I2C3 92
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#define SRST_P_I2C5 93
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#define SRST_I2C5 94
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#define SRST_P_I2C6 95
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#define SRST_I2C6 96
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#define SRST_A_MAC 97
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#define SRST_P_PCIE 98
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#define SRST_PCIE_PIPE_PHY 99
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#define SRST_PCIE_POWER_UP 100
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#define SRST_P_PCIE_PHY 101
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#define SRST_P_PIPE_GRF 102
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#define SRST_H_SDIO0 103
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#define SRST_H_SDIO1 104
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#define SRST_TS_0 105
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#define SRST_TS_1 106
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#define SRST_P_CAN2 107
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#define SRST_CAN2 108
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#define SRST_P_CAN3 109
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#define SRST_CAN3 110
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#define SRST_P_SARADC 111
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#define SRST_SARADC 112
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#define SRST_SARADC_PHY 113
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#define SRST_P_TSADC 114
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#define SRST_TSADC 115
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#define SRST_A_USB3OTG 116
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#define SRST_A_GPU_BIU 117
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#define SRST_P_GPU_BIU 118
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#define SRST_A_GPU 119
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#define SRST_REF_PVTPLL_GPU 120
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#define SRST_H_RKVENC_BIU 121
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#define SRST_A_RKVENC_BIU 122
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#define SRST_P_RKVENC_BIU 123
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#define SRST_H_RKVENC 124
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#define SRST_A_RKVENC 125
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#define SRST_CORE_RKVENC 126
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#define SRST_H_SAI_I2S1 127
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#define SRST_M_SAI_I2S1 128
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#define SRST_P_I2C1 129
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#define SRST_I2C1 130
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#define SRST_P_I2C0 131
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#define SRST_I2C0 132
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#define SRST_P_SPI0 133
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#define SRST_SPI0 134
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#define SRST_P_GPIO4 135
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#define SRST_DB_GPIO4 136
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#define SRST_P_RKVENC_IOC 137
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#define SRST_H_SPDIF 138
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#define SRST_M_SPDIF 139
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#define SRST_H_PDM 140
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#define SRST_M_PDM 141
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#define SRST_P_UART1 142
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#define SRST_S_UART1 143
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#define SRST_P_UART3 144
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#define SRST_S_UART3 145
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#define SRST_P_RKVENC_GRF 146
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#define SRST_P_CAN0 147
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#define SRST_CAN0 148
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#define SRST_P_CAN1 149
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#define SRST_CAN1 150
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#define SRST_A_VO_BIU 151
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#define SRST_H_VO_BIU 152
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#define SRST_P_VO_BIU 153
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#define SRST_H_RGA2E 154
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#define SRST_A_RGA2E 155
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#define SRST_CORE_RGA2E 156
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#define SRST_H_VDPP 157
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#define SRST_A_VDPP 158
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#define SRST_CORE_VDPP 159
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#define SRST_P_VO_GRF 160
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#define SRST_P_CRU 161
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#define SRST_A_VOP_BIU 162
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#define SRST_H_VOP 163
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#define SRST_D_VOP0 164
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#define SRST_D_VOP1 165
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#define SRST_A_VOP 166
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#define SRST_P_HDMI 167
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#define SRST_HDMI 168
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#define SRST_P_HDMIPHY 169
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#define SRST_H_HDCP_KEY 170
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#define SRST_A_HDCP 171
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#define SRST_H_HDCP 172
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#define SRST_P_HDCP 173
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#define SRST_H_CVBS 174
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#define SRST_D_CVBS_VOP 175
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#define SRST_D_4X_CVBS_VOP 176
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#define SRST_A_JPEG_DECODER 177
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#define SRST_H_JPEG_DECODER 178
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#define SRST_A_VO_L_BIU 179
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#define SRST_A_MAC_VO 180
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#define SRST_A_JPEG_BIU 181
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#define SRST_H_SAI_I2S3 182
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#define SRST_M_SAI_I2S3 183
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#define SRST_MACPHY 184
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#define SRST_P_VCDCPHY 185
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#define SRST_P_GPIO2 186
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#define SRST_DB_GPIO2 187
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#define SRST_P_VO_IOC 188
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#define SRST_H_SDMMC0 189
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#define SRST_P_OTPC_NS 190
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#define SRST_SBPI_OTPC_NS 191
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#define SRST_USER_OTPC_NS 192
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#define SRST_HDMIHDP0 193
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#define SRST_H_USBHOST 194
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#define SRST_H_USBHOST_ARB 195
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#define SRST_HOST_UTMI 196
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#define SRST_P_UART4 197
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#define SRST_S_UART4 198
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#define SRST_P_I2C4 199
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#define SRST_I2C4 200
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#define SRST_P_I2C7 201
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#define SRST_I2C7 202
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#define SRST_P_USBPHY 203
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#define SRST_USBPHY_POR 204
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#define SRST_USBPHY_OTG 205
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#define SRST_USBPHY_HOST 206
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#define SRST_P_DDRPHY_CRU 207
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#define SRST_H_RKVDEC_BIU 208
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#define SRST_A_RKVDEC_BIU 209
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#define SRST_A_RKVDEC 210
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#define SRST_H_RKVDEC 211
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#define SRST_HEVC_CA_RKVDEC 212
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#define SRST_REF_PVTPLL_RKVDEC 213
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#define SRST_P_DDR_BIU 214
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#define SRST_P_DDRC 215
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#define SRST_P_DDRMON 216
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#define SRST_TIMER_DDRMON 217
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#define SRST_P_MSCH_BIU 218
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#define SRST_P_DDR_GRF 219
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#define SRST_P_DDR_HWLP 220
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#define SRST_P_DDRPHY 221
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#define SRST_MSCH_BIU 222
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#define SRST_A_DDR_UPCTL 223
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#define SRST_DDR_UPCTL 224
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#define SRST_DDRMON 225
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#define SRST_A_DDR_SCRAMBLE 226
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#define SRST_A_SPLIT 227
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#define SRST_DDR_PHY 228
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#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
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