53 lines
2.2 KiB
JSON
53 lines
2.2 KiB
JSON
[
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{
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"ArchStdEvent": "L1I_CACHE_REFILL",
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"BriefDescription": "This event counts operations that cause a refill of the L1I cache. See L1I_CACHE_REFILL of ARMv9 Reference Manual for more information."
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},
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{
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"ArchStdEvent": "L1I_CACHE",
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"BriefDescription": "This event counts operations that cause a cache access to the L1I cache. See L1I_CACHE of ARMv9 Reference Manual for more information."
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},
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{
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"EventCode": "0x0207",
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"EventName": "L1I_CACHE_DM_RD",
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"BriefDescription": "This event counts L1I_CACHE caused by demand read access."
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},
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{
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"EventCode": "0x020F",
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"EventName": "L1I_CACHE_REFILL_DM_RD",
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"BriefDescription": "This event counts L1I_CACHE_REFILL caused by demand read access."
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},
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{
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"ArchStdEvent": "L1I_CACHE_LMISS",
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"BriefDescription": "This event counts operations that cause a refill of the L1I cache that incurs additional latency."
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},
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{
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"ArchStdEvent": "L1I_CACHE_HWPRF",
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"BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch."
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL_HWPRF",
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"BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch."
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},
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{
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"ArchStdEvent": "L1I_CACHE_HIT_RD",
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"BriefDescription": "This event counts demand fetch counted by L1I_CACHE_DM_RD that hits in the Level 1 instruction cache."
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},
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{
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"ArchStdEvent": "L1I_CACHE_HIT",
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"BriefDescription": "This event counts access counted by L1I_CACHE that hits in the Level 1 instruction cache."
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},
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{
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"ArchStdEvent": "L1I_LFB_HIT_RD",
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"BriefDescription": "This event counts demand access counted by L1I_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 instruction cache."
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL_PRF",
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"BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch or software prefetch."
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL_PERCYC",
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"BriefDescription": "This counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
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}
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]
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