Linux-6.18.2/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
2025-12-23 20:06:59 +08:00

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[
{
"EventName": "ICACHE_MISS",
"EventCode": "0x102",
"BriefDescription": "Counts instruction cache misses"
},
{
"EventName": "DCACHE_MISS",
"EventCode": "0x202",
"BriefDescription": "Counts data cache misses"
},
{
"EventName": "DCACHE_RELEASE",
"EventCode": "0x402",
"BriefDescription": "Counts writeback requests from the data cache"
},
{
"EventName": "ITLB_MISS",
"EventCode": "0x802",
"BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
},
{
"EventName": "DTLB_MISS",
"EventCode": "0x1002",
"BriefDescription": "Counts Data TLB misses caused by data address translation requests"
},
{
"EventName": "UTLB_MISS",
"EventCode": "0x2002",
"BriefDescription": "Counts Unified TLB misses caused by address translation requests"
},
{
"EventName": "UTLB_HIT",
"EventCode": "0x4002",
"BriefDescription": "Counts Unified TLB hits for address translation requests"
},
{
"EventName": "PTE_CACHE_MISS",
"EventCode": "0x8002",
"BriefDescription": "Counts Page Table Entry cache misses"
},
{
"EventName": "PTE_CACHE_HIT",
"EventCode": "0x10002",
"BriefDescription": "Counts Page Table Entry cache hits"
}
]