78 lines
3.9 KiB
C
78 lines
3.9 KiB
C
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/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_RSWDT_COMPONENT_
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#define _SAME70_RSWDT_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */
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/* ============================================================================= */
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/** \addtogroup SAME70_RSWDT Reinforced Safety Watchdog Timer */
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/*@{*/
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief Rswdt hardware registers */
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typedef struct {
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__O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */
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__IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */
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__I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */
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} Rswdt;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */
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#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */
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#define RSWDT_CR_KEY_Pos 24
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#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */
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#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))
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#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */
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/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */
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#define RSWDT_MR_WDV_Pos 0
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#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */
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#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))
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#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */
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#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */
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#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */
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#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */
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#define RSWDT_MR_ALLONES_Pos 16
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#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */
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#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)))
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#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */
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#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */
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/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */
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#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */
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/*@}*/
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#endif /* _SAME70_RSWDT_COMPONENT_ */
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