96 lines
7.6 KiB
C
96 lines
7.6 KiB
C
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/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_ISI_INSTANCE_
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#define _SAME70_ISI_INSTANCE_
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/* ========== Register definition for ISI peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */
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#define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */
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#define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */
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#define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
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#define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
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#define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
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#define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
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#define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
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#define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
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#define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */
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#define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */
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#define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */
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#define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */
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#define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */
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#define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */
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#define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */
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#define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */
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#define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */
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#define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */
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#define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
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#define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */
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#define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */
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#define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
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#define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */
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#define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */
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#define REG_ISI_VERSION (0x4004C0FCU) /**< \brief (ISI) Version Register */
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#else
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#define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */
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#define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */
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#define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */
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#define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
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#define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
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#define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
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#define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
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#define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
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#define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
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#define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */
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#define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */
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#define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */
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#define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */
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#define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */
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#define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */
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#define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */
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#define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */
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#define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */
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#define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */
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#define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
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#define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */
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#define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */
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#define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
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#define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */
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#define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */
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#define REG_ISI_VERSION (*(__I uint32_t*)0x4004C0FCU) /**< \brief (ISI) Version Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_ISI_INSTANCE_ */
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