80 lines
5.4 KiB
C
80 lines
5.4 KiB
C
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/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_TWIHS1_INSTANCE_
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#define _SAME70_TWIHS1_INSTANCE_
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/* ========== Register definition for TWIHS1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */
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#define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
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#define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
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#define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
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#define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
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#define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */
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#define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
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#define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
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#define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
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#define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
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#define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
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#define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
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#define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */
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#define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
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#define REG_TWIHS1_DR (0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */
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#define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
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#define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
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#define REG_TWIHS1_VER (0x4001C0FCU) /**< \brief (TWIHS1) Version Register */
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#else
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#define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */
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#define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
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#define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
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#define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
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#define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
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#define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */
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#define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
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#define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
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#define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
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#define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
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#define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
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#define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
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#define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */
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#define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
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#define REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */
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#define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
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#define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
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#define REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU) /**< \brief (TWIHS1) Version Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_TWIHS1_INSTANCE_ */
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