78 lines
5.2 KiB
C
78 lines
5.2 KiB
C
/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_QSPI_INSTANCE_
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#define _SAME70_QSPI_INSTANCE_
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/* ========== Register definition for QSPI peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */
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#define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */
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#define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */
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#define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */
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#define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */
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#define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */
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#define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */
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#define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */
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#define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */
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#define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */
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#define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */
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#define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */
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#define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */
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#define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */
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#define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */
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#define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */
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#define REG_QSPI_VERSION (0x4007C0FCU) /**< \brief (QSPI) Version Register */
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#else
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#define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */
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#define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */
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#define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */
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#define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */
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#define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */
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#define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */
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#define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */
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#define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */
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#define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */
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#define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */
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#define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */
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#define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */
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#define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */
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#define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */
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#define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */
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#define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */
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#define REG_QSPI_VERSION (*(__I uint32_t*)0x4007C0FCU) /**< \brief (QSPI) Version Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_QSPI_INSTANCE_ */
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