72 lines
4.8 KiB
C
72 lines
4.8 KiB
C
/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_SDRAMC_INSTANCE_
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#define _SAME70_SDRAMC_INSTANCE_
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/* ========== Register definition for SDRAMC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */
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#define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
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#define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
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#define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
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#define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
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#define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
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#define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
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#define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
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#define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
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#define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
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#define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */
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#define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */
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#define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */
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#define REG_SDRAMC_VERSION (0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */
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#else
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#define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */
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#define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
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#define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
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#define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
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#define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
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#define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
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#define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
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#define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
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#define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
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#define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
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#define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */
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#define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */
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#define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */
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#define REG_SDRAMC_VERSION (*(__I uint32_t*)0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_SDRAMC_INSTANCE_ */
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