82 lines
5.6 KiB
C
82 lines
5.6 KiB
C
/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_SSC_INSTANCE_
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#define _SAME70_SSC_INSTANCE_
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/* ========== Register definition for SSC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */
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#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */
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#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
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#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
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#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
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#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
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#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */
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#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
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#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
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#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
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#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
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#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
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#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */
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#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
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#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
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#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
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#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
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#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
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#define REG_SSC_VERSION (0x400040FCU) /**< \brief (SSC) Version Register */
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#else
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#define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */
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#define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
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#define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
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#define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
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#define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
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#define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
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#define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
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#define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
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#define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
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#define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
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#define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
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#define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
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#define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */
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#define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
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#define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
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#define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
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#define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
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#define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
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#define REG_SSC_VERSION (*(__I uint32_t*)0x400040FCU) /**< \brief (SSC) Version Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_SSC_INSTANCE_ */
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