108 lines
8.5 KiB
C
108 lines
8.5 KiB
C
/**
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* \file
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef _SAME70_USART0_INSTANCE_
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#define _SAME70_USART0_INSTANCE_
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/* ========== Register definition for USART0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */
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#define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */
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#define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
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#define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
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#define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
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#define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */
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#define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */
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#define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
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#define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
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#define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
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#define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
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#define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
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#define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */
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#define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
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#define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
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#define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */
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#define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */
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#define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
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#define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */
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#define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */
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#define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */
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#define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
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#define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */
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#define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
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#define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
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#define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */
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#define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
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#define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
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#define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */
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#define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
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#define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
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#define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */
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#else
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#define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */
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#define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */
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#define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
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#define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
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#define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
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#define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */
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#define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */
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#define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
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#define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
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#define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
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#define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
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#define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
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#define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
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#define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
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#define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
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#define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */
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#define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */
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#define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
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#define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */
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#define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */
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#define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */
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#define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
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#define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */
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#define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
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#define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
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#define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */
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#define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
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#define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
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#define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */
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#define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
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#define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
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#define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) /**< \brief (USART0) Version Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_USART0_INSTANCE_ */
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