jzh/lark1s_demo
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[feat] add basic usart for dwin

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This commit is contained in:
zhji 2024-07-07 21:37:22 +08:00
parent 283685ff35
commit b5c3737eeb
5 changed files with 205 additions and 2 deletions
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3
stm32f4/main.c
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@ -2,6 +2,7 @@
#include "led.h"
// #include "lcd.h"
#include "rs485.h"
#include "dwin.h"
volatile uint32_t system_tick_cnt;
@ -31,6 +32,7 @@ void system_init(void)
system_tick_init();
// lcd_init();
rs485_init();
dwin_init();
}
int main(void)
@ -43,6 +45,7 @@ int main(void)
led_loop();
// lcd_loop();
rs485_loop();
dwin_loop();
}
return 0;
}

1
stm32f4/src/CMakeLists.txt
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@ -2,6 +2,7 @@ file(GLOB FILELIST
led.c
# lcd.c
rs485.c
dwin.c
)
add_library(src STATIC ${FILELIST})

132
stm32f4/src/dwin.c Normal file
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@ -0,0 +1,132 @@
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_usart.h"
#include "stm32f4xx_dma.h"
#include "dwin.h"
#define DWIN_TX_STREAM DMA1_Stream6
#define DWIN_RX_STREAM DMA1_Stream5
#define DWIN_BUFF_TX_LEN (4096)
#define DWIN_BUFF_RX_LEN (4096)
uint8_t dwin_buff_tx[DWIN_BUFF_TX_LEN] __attribute__((aligned(16)));
uint8_t dwin_buff_rx[DWIN_BUFF_RX_LEN] __attribute__((aligned(16)));
extern uint32_t system_tick_cnt;
void dwin_init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
USART_InitTypeDef USART_InitStructure;
DMA_InitTypeDef DMA_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
GPIO_PinAFConfig(DWIN_PORT, GPIO_PinSource2, GPIO_AF_USART2);
GPIO_PinAFConfig(DWIN_PORT, GPIO_PinSource3, GPIO_AF_USART2);
GPIO_InitStructure.GPIO_Pin = DWIN_PIN_TX | DWIN_PIN_RX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(DWIN_PORT, &GPIO_InitStructure);
USART_DeInit(USART2);
USART_OverSampling8Cmd(USART2, ENABLE);
USART_InitStructure.USART_BaudRate = DWIN_BAUDRATE;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART2, &USART_InitStructure);
USART_DMACmd(USART2, USART_DMAReq_Tx, ENABLE);
USART_DMACmd(USART2, USART_DMAReq_Rx, ENABLE);
USART_Cmd(USART2, ENABLE);
DMA_InitStructure.DMA_BufferSize = DWIN_BUFF_TX_LEN;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_PeripheralBaseAddr =(uint32_t)(&(USART2->DR));
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
DMA_InitStructure.DMA_Channel = DMA_Channel_4;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dwin_buff_tx;
DMA_Init(DWIN_TX_STREAM, &DMA_InitStructure);
/* Configure DMA controller to manage USART RX request */
DMA_InitStructure.DMA_BufferSize = DWIN_BUFF_RX_LEN;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dwin_buff_rx;
DMA_Init(DWIN_RX_STREAM, &DMA_InitStructure);
/* Configure interrupt for USART2 RX */
NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 12;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
USART_ITConfig(USART2, USART_IT_IDLE, ENABLE);
USART_ITConfig(USART2, USART_IT_TC, ENABLE);
/* clear IT flag */
USART_GetITStatus(USART2, USART_IT_IDLE);
USART_ReceiveData(USART2);
USART_ClearITPendingBit(USART2, USART_IT_IDLE);
USART_ClearITPendingBit(USART2, USART_IT_TC);
dwin_send(5);
}
void dwin_send(uint16_t len)
{
DMA_SetCurrDataCounter(DWIN_TX_STREAM, len);
DMA_Cmd(DWIN_TX_STREAM, ENABLE);
}
void dwin_loop(void)
{
static uint32_t ms = 0;
if (system_tick_cnt < (ms + 500)) {
return;
}
ms = system_tick_cnt;
}
void USART2_IRQHandler(void)
{
uint16_t len;
if (USART_GetITStatus(USART2, USART_IT_TC) != RESET)
{
USART_ClearITPendingBit(USART2, USART_IT_TC);
DMA_ClearFlag(DWIN_TX_STREAM, DMA_FLAG_TCIF6 | DMA_FLAG_HTIF6 | DMA_FLAG_TEIF6 | DMA_FLAG_DMEIF6 | DMA_FLAG_FEIF6);
DMA_Cmd(DWIN_TX_STREAM, DISABLE);
/* after tx complete, config rx */
USART_ReceiveData(USART2);
USART_ClearITPendingBit(USART2, USART_IT_IDLE);
DMA_SetCurrDataCounter(DWIN_RX_STREAM, DWIN_BUFF_RX_LEN);
DMA_Cmd(DWIN_RX_STREAM, ENABLE);
USART_ITConfig(USART2, USART_IT_IDLE, ENABLE);
}
if (USART_GetITStatus(USART2, USART_IT_IDLE) != RESET) {
USART_ITConfig(USART2, USART_IT_IDLE, DISABLE);
USART_ReceiveData(USART2);
USART_ClearITPendingBit(USART2, USART_IT_IDLE);
DMA_Cmd(DWIN_RX_STREAM, DISABLE);
DMA_ClearFlag(DWIN_RX_STREAM, DMA_FLAG_TCIF5 | DMA_FLAG_HTIF5 | DMA_FLAG_TEIF5 | DMA_FLAG_DMEIF5 | DMA_FLAG_FEIF5);
len = DMA_GetCurrDataCounter(DWIN_RX_STREAM);
len = DWIN_BUFF_RX_LEN - len;
for (uint16_t i = 0; i < len; i++) {
dwin_buff_tx[i] = dwin_buff_rx[i] + 1;
}
dwin_send(len);
}
}

57
stm32f4/src/dwin.h Normal file
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@ -0,0 +1,57 @@
#ifndef __RS485_H__
#define __RS485_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32f4xx.h"
#define DWIN_PORT (GPIOA)
#define DWIN_PIN_TX (GPIO_Pin_2)
#define DWIN_PIN_RX (GPIO_Pin_3)
#define DWIN_BAUDRATE (115200)
struct dwin_ctrl_s {
uint32_t baudrate;
uint32_t cali_conc;
uint8_t cali_active;
uint8_t cali_restore;
uint8_t mb_addr;
};
struct dwin_info_s {
uint8_t gas_name[16];
uint8_t sn[16];
uint32_t concentration;
uint8_t conc_unit[16];
uint32_t det_temp;
uint32_t sig_cts;
uint32_t ref_cts;
uint32_t air_pressure;
uint32_t range;
uint32_t mini_cali;
uint16_t sts_zero;
uint16_t sts_span;
uint16_t sts_active;
uint16_t sts_restore;
uint16_t cali_zero_enable;
uint16_t cali_zero_temp;
uint32_t cali_zero_sig;
uint32_t cali_zero_ref;
uint16_t cali_span_enable;
uint16_t cali_span_temp;
uint32_t cali_span_conc;
uint32_t cali_span_sig;
uint32_t cali_span_ref;
};
void dwin485_init(void);
void dwin_send(uint16_t len);
void dwin_loop(void);
#ifdef __cplusplus
}
#endif
#endif /* __RS485_H__ */

14
stm32f4/src/rs485.c
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@ -7,7 +7,7 @@
#define RS485_TX_STREAM DMA1_Stream3
#define RS485_RX_STREAM DMA1_Stream1
#define RS485_BUFF_TX_LEN (4096)
#define RS485_BUFF_RX_LEN (1024)
#define RS485_BUFF_RX_LEN (4096)
uint8_t rs485_buff_tx[RS485_BUFF_TX_LEN] __attribute__((aligned(16)));
uint8_t rs485_buff_rx[RS485_BUFF_RX_LEN] __attribute__((aligned(16)));
@ -99,7 +99,7 @@ void rs485_init(void)
USART_ClearITPendingBit(USART3, USART_IT_IDLE);
USART_ClearITPendingBit(USART3, USART_IT_TC);
rs485_send(15);
// rs485_send(15);
}
void rs485_send(uint16_t len)
@ -109,6 +109,16 @@ void rs485_send(uint16_t len)
DMA_Cmd(RS485_TX_STREAM, ENABLE);
}
void modbus_get_sn(void)
{
}
void modbus_get_info(void)
{
}
void rs485_loop(void)
{
static uint32_t ms = 0;