2025-04-19 21:07:29 +08:00
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#ifndef __HARDWARE_SSI_REG_H__
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#define __HARDWARE_SSI_REG_H__
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#include "reg.h"
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2025-05-10 17:20:09 +08:00
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#define SSI_CTRLR0_TMOD_POS (8U)
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#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX_MASK (0x0 << SSI_CTRLR0_TMOD_POS)
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#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY_MASK (0x1 << SSI_CTRLR0_TMOD_POS)
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#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY_MASK (0x2 << SSI_CTRLR0_TMOD_POS)
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#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ_MASK (0x3 << SSI_CTRLR0_TMOD_POS)
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#define SSI_CTRLR0_DFS_32_POS (16U)
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#define SSI_CTRLR0_SPI_FRF_POS (21U)
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#define SSI_CTRLR0_SPI_FRF_VALUE_STD_MASK (0x0 << SSI_CTRLR0_SPI_FRF_POS)
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#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL_MASK (0x1 << SSI_CTRLR0_SPI_FRF_POS)
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#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD_MASK (0x2 << SSI_CTRLR0_SPI_FRF_POS)
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#define SSI_SPI_CTRLR0_TRANS_TYPE_POS (0U)
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#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A_MASK (0x0 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
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#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A_MASK (0x1 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
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#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A_MASK (0x2 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
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#define SSI_SPI_CTRLR0_ADDR_L_POS (2U)
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#define SSI_SPI_CTRLR0_INST_L_POS (8U)
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#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE_MASK (0x0 << SSI_SPI_CTRLR0_INST_L_POS)
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#define SSI_SPI_CTRLR0_INST_L_VALUE_4B_MASK (0x1 << SSI_SPI_CTRLR0_INST_L_POS)
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#define SSI_SPI_CTRLR0_INST_L_VALUE_8B_MASK (0x2 << SSI_SPI_CTRLR0_INST_L_POS)
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#define SSI_SPI_CTRLR0_INST_L_VALUE_16_MASKB (0x3 << SSI_SPI_CTRLR0_INST_L_POS)
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#define SSI_SPI_CTRLR0_WAIT_CYCLES_POS (11U)
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#define SSI_SPI_CTRLR0_XIP_CMD_POS (24U)
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#define SSI_SR_BUSY (1 << 0)
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#define SSI_SR_TFNF (1 << 1)
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#define SSI_SR_TFE (1 << 2)
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#define SSI_SR_RFNE (1 << 3)
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#define SSI_SR_RFF (1 << 4)
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#define SSI_SR_TXE (1 << 5)
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#define SSI_SR_DCOL (1 << 6)
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2025-04-19 21:07:29 +08:00
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typedef struct {
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io_rw_32 ctrlr0;
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io_rw_32 ctrlr1;
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io_rw_32 ssienr;
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io_rw_32 mwcr;
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io_rw_32 ser;
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io_rw_32 baudr;
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io_rw_32 txftlr;
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io_rw_32 rxftlr;
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io_rw_32 txflr;
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io_rw_32 rxflr;
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io_rw_32 sr;
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io_rw_32 imr;
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io_rw_32 isr;
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io_rw_32 risr;
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io_rw_32 txoicr;
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io_rw_32 rxoicr;
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io_rw_32 rxuicr;
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io_rw_32 msticr;
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io_rw_32 icr;
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io_rw_32 dmacr;
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io_rw_32 dmatdlr;
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io_rw_32 dmardlr;
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io_rw_32 idr;
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io_rw_32 ssi_version_id;
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io_rw_32 dr0;
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uint32_t _pad[(0xf0 - 0x60) / 4 - 1];
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io_rw_32 rx_sample_dly;
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io_rw_32 spi_ctrlr0;
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io_rw_32 txd_drive_edge;
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} ssi_hw_t;
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#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE)
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#define ssi_hw_set ((ssi_hw_t *const)hw_set_alias_untyped(ssi_hw))
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#define ssi_hw_clear ((ssi_hw_t *const)hw_clear_alias_untyped(ssi_hw))
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HARDWARE_SSI_REG_H__ */
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