102 lines
5.2 KiB
C
102 lines
5.2 KiB
C
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#ifndef __HARDWARE_GPIO_REG_H__
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#define __HARDWARE_GPIO_REG_H__
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/* IO_BANK0_BASE @0x40014000 */
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#define GPIO_STATUS_OFFSET (0x000)
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#define GPIO_CTRL_OFFSET (0x004)
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#define GPIO_INTR_OFFSET (0x0F0) /* raw interrupts */
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#define GPIO_INTE_PROC0_OFFSET (0x100) /* interrupt enable for proc0 */
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#define GPIO_INTF_PROC0_OFFSET (0x110) /* interrupt force for proc0 */
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#define GPIO_INTS_PROC0_OFFSET (0x120) /* interrupt status after masking & forcing for proc0 */
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#define GPIO_INTE_PROC1_OFFSET (0x130) /* interrupt enable for proc1 */
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#define GPIO_INTF_PROC1_OFFSET (0x140) /* interrupt force for proc1 */
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#define GPIO_INTS_PROC1_OFFSET (0x150) /* interrupt status after masking & forcing for proc1 */
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#define GPIO_INTE_DORMANT_WAKE_OFFSET (0x160) /* interrupt enable for dormant_wake */
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#define GPIO_INTF_DORMANT_WAKE_OFFSET (0x170) /* interrupt force for dormant_wake */
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#define GPIO_INTS_DORMANT_WAKE_OFFSET (0x180) /* interrupt status after masking & forcing for dormant_wake */
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/* IO_QSPI_BASE @0x40018000 */
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#define GPIO_QSPI_CLK_STATUS_OFFSET (0x000) /* QSPI CLK GPIO status */
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#define GPIO_QSPI_CLK_CTRL_OFFSET (0x004) /* QSPI CLK GPIO control including function select and overrides */
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#define GPIO_QSPI_CS_STATUS_OFFSET (0x008) /* QSPI CS GPIO status */
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#define GPIO_QSPI_CS_CTRL_OFFSET (0x00C) /* QSPI CS GPIO control including function select and overrides */
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#define GPIO_QSPI_IO0_STATUS_OFFSET (0x010) /* QSPI IO0 GPIO status */
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#define GPIO_QSPI_IO0_CTRL_OFFSET (0x014) /* QSPI IO0 GPIO control including function select and overrides */
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#define GPIO_QSPI_IO1_STATUS_OFFSET (0x018) /* QSPI IO1 GPIO status */
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#define GPIO_QSPI_IO1_CTRL_OFFSET (0x01C) /* QSPI IO1 GPIO control including function select and overrides */
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#define GPIO_QSPI_IO2_STATUS_OFFSET (0x020) /* QSPI IO2 GPIO status */
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#define GPIO_QSPI_IO2_CTRL_OFFSET (0x024) /* QSPI IO2 GPIO control including function select and overrides */
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#define GPIO_QSPI_IO3_STATUS_OFFSET (0x028) /* QSPI IO3 GPIO status */
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#define GPIO_QSPI_IO3_CTRL_OFFSET (0x02C) /* QSPI IO3 GPIO control including function select and overrides */
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#define GPIO_QSPI_INTR_OFFSET (0x030) /* raw interrupts */
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#define GPIO_QSPI_INTE_PROC0_OFFSET (0x034) /* interrupt enable for proc0 */
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#define GPIO_QSPI_INTF_PROC0_OFFSET (0x038) /* interrupt force for proc0 */
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#define GPIO_QSPI_INTS_PROC0_OFFSET (0x03C) /* interrupt status after masking & forcing for proc0 */
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#define GPIO_QSPI_INTE_PROC1_OFFSET (0x040) /* interrupt enable for proc1 */
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#define GPIO_QSPI_INTF_PROC1_OFFSET (0x044) /* interrupt force for proc1 */
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#define GPIO_QSPI_INTS_PROC1_OFFSET (0x048) /* interrupt status after masking & forcing for proc1 */
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#define GPIO_QSPI_INTE_DORMANT_WAKE_OFFSET (0x04C) /* interrupt enable for dormant_wake */
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#define GPIO_QSPI_INTF_DORMANT_WAKE_OFFSET (0x050) /* interrupt force for dormant_wake */
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#define GPIO_QSPI_INTS_DORMANT_WAKE_OFFSET (0x054) /* interrupt status after masking & forcing for dormant_wake */
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/* PADS_BANK0_BASE @0x4001C000 */
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#define GPIO_PADS_VOLTAGE_SELECT_OFFSET (0x000)
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#define GPIO_PADS_CTRL_OFFSET (0x004) /* pad control register */
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#define GPIO_PADS_SWCLK_CTRL_OFFSET (0x07C)
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#define GPIO_PADS_SWDIO_CTRL_OFFSET (0x080)
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/* PADS_QSPI_BASE @0x40020000 */
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#define GPIO_PADS_QSPI_VOLTAGE_SELECT_OFFSET (0x000)
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#define GPIO_PADS_QSPI_CLK_CTRL_OFFSET (0x004)
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#define GPIO_PADS_QSPI_IO0_CTRL_OFFSET (0x008)
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#define GPIO_PADS_QSPI_IO1_CTRL_OFFSET (0x00C)
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#define GPIO_PADS_QSPI_IO2_CTRL_OFFSET (0x010)
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#define GPIO_PADS_QSPI_IO3_CTRL_OFFSET (0x014)
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#define GPIO_PADS_QSPI_CS_CTRL_OFFSET (0x018)
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/* GPIO_STATUS_OFFSET */
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#define GPIO_STATUS_OE_FROM_PERI (1 << 12)
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#define GPIO_STATUS_OE_TO_PAD (1 << 13)
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#define GPIO_STATUS_IN_FROM_PAD (1 << 17)
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#define GPIO_STATUS_IN_TO_PERI (1 << 19)
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#define GPIO_STATUS_IRQ_FROM_PAD (1 << 24)
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#define GPIO_STATUS_IRQ_TO_PROC (1 << 26)
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#define GPIO_STATUS_ALL (GPIO_STATUS_OE_FROM_PERI | \
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GPIO_STATUS_OE_TO_PAD | \
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GPIO_STATUS_IN_FROM_PAD | \
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GPIO_STATUS_IN_TO_PERI | \
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GPIO_STATUS_IRQ_FROM_PAD | \
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GPIO_STATUS_IRQ_TO_PROC)
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/* GPIO_CTRL_OFFSET */
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#define GPIO_FUNC_POS (0)
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#define GPIO_FUNC_MASK (0x1F)
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#define GPIO_OVER_OUT_POS (8)
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#define GPIO_OVER_OUT_MASK (3)
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#define GPIO_OVER_OE_POS (12)
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#define GPIO_OVER_OE_MASK (3)
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#define GPIO_OVER_IN_POS (16)
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#define GPIO_OVER_IN_MASK (3)
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#define GPIO_OVER_IRQ_POS (28)
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#define GPIO_OVER_IRQ_MASK (3)
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/* GPIO_PADS_CTRL_OFFSET */
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#define GPIO_PADS_SLEW_RATE_POS (0)
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#define GPIO_PADS_SCHMITT_POS (1)
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#define GPIO_PADS_PULL_DOWN_POS (2)
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#define GPIO_PADS_PULL_UP_POS (3)
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#define GPIO_PADS_DRIVE_POS (4)
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#define GPIO_PADS_DRIVE_MASK (3)
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#define GPIO_PADS_IE_POS (6)
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#define GPIO_PADS_OD_POS (7)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HARDWARE_GPIO_REG_H__ */
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