2025-03-19 15:59:12 +08:00
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#ifndef __UART_REG_H__
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#define __UART_REG_H__
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#define UART_UARTDR_OFFSET (0x000)
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#define UART_UARTRSR_OFFSET (0x004)
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#define UART_UARTFR_OFFSET (0x018)
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#define UART_UARTILPR_OFFSET (0x020)
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#define UART_UARTIBRD_OFFSET (0x024)
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#define UART_UARTFBRD_OFFSET (0x028)
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#define UART_UARTLCR_H_OFFSET (0x02C)
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#define UART_UARTCR_OFFSET (0x030)
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#define UART_UARTIFLS_OFFSET (0x034)
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#define UART_UARTIMSC_OFFSET (0x038)
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#define UART_UARTRIS_OFFSET (0x03C)
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#define UART_UARTMIS_OFFSET (0x040)
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#define UART_UARTICR_OFFSET (0x044)
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#define UART_UARTDMACR_OFFSET (0x048)
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#define UART_UARTPERIPHID0_OFFSET (0xFE0)
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#define UART_UARTPERIPHID1_OFFSET (0xFE4)
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#define UART_UARTPERIPHID2_OFFSET (0xFE8)
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#define UART_UARTPERIPHID3_OFFSET (0xFEC)
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#define UART_UARTPCELLID0 (0xFF0)
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#define UART_UARTPCELLID1 (0xFF4)
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#define UART_UARTPCELLID2 (0xFF8)
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#define UART_UARTPCELLID3 (0xFFC)
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/* UART_UARTDR_OFFSET @0x000 */
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#define UART_UARTDR_DATA_POS (0U)
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#define UART_UARTDR_DATA_MASK (0xFF << UART_UARTDR_DATA_POS)
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#define UART_UARTDR_FE (1 << 8U)
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#define UART_UARTDR_PE (1 << 9U)
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#define UART_UARTDR_BE (1 << 10U)
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#define UART_UARTDR_OE (1 << 11U)
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/* UART_UARTRSR_OFFSET @0x004 */
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#define UART_UARTRSR_FE (1 << 0U)
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#define UART_UARTRSR_PE (1 << 1U)
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#define UART_UARTRSR_BE (1 << 2U)
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#define UART_UARTRSR_OE (1 << 3U)
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/* UART_UARTFR_OFFSET @0x018 */
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#define UART_UARTFR_CTS (1 << 0U)
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#define UART_UARTFR_DSR (1 << 1U)
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#define UART_UARTFR_DCD (1 << 2U)
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#define UART_UARTFR_BUSY (1 << 3U)
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#define UART_UARTFR_RXFE (1 << 4U)
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#define UART_UARTFR_TXFF (1 << 5U)
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#define UART_UARTFR_RXFF (1 << 6U)
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#define UART_UARTFR_TXFE (1 << 7U)
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#define UART_UARTFR_RI (1 << 8U)
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/* UART_UARTILPR_OFFSET @0x020 */
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#define UART_UARTILPR_ILPDVSR_POS (0U)
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#define UART_UARTILPR_ILPDVSR_MASK (0xFF << UART_UARTILPR_ILPDVSR_POS)
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/* UART_UARTIBRD_OFFSET @0x024 */
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#define UART_UARTIBRD_BAUD_DIVINT_POS (0U)
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#define UART_UARTIBRD_BAUD_DIVINT_MASK (0xFFFF << UART_UARTIBRD_BAUD_DIVINT_POS)
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/* UART_UARTFBRD_OFFSET @0x028 */
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#define UART_UARTFBRD_BAUD_DIVFRAC_POS (0U)
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#define UART_UARTFBRD_BAUD_DIVFRAC_MASK (0x3F << UART_UARTFBRD_BAUD_DIVFRAC_POS)
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/* UART_UARTLCR_H_OFFSET @0x02C */
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#define UART_UARTLCR_H_BRK (1 << 0U)
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#define UART_UARTLCR_H_PEN (1 << 1U)
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#define UART_UARTLCR_H_EPS (1 << 2U)
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#define UART_UARTLCR_H_STP2 (1 << 3U)
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#define UART_UARTLCR_H_FEN (1 << 4U)
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#define UART_UARTLCR_H_WLEN_POS (5U)
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#define UART_UARTLCR_H_WLEN_MASK (0x3 << UART_UARTLCR_H_WLEN_POS)
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#define UART_UARTLCR_H_SPS (1 << 7U)
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/* UART_UARTCR_OFFSET @0x030 */
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#define UART_UARTCR_UARTEN (1 << 0U)
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#define UART_UARTCR_SIREN (1 << 1U)
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#define UART_UARTCR_SIRLP (1 << 2U)
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#define UART_UARTCR_LBE (1 << 7U)
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#define UART_UARTCR_TXE (1 << 8U)
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#define UART_UARTCR_RXE (1 << 9U)
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#define UART_UARTCR_DTR (1 << 10U)
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#define UART_UARTCR_RTS (1 << 11U)
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#define UART_UARTCR_OUT1 (1 << 12U)
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#define UART_UARTCR_OUT2 (1 << 13U)
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#define UART_UARTCR_RTSEN (1 << 14U)
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#define UART_UARTCR_CTSEN (1 << 15U)
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/* UART_UARTIFLS_OFFSET @0x034 */
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#define UART_UARTIFLS_TXIFLSEL_POS (0U)
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#define UART_UARTIFLS_TXIFLSEL_MASK (0x7 << UART_UARTIFLS_TXIFLSEL_POS)
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#define UART_UARTIFLS_RXIFLSEL_POS (3U)
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2025-03-19 21:53:54 +08:00
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#define UART_UARTIFLS_RXIFLSEL_MASK (0x7 << UART_UARTIFLS_RXIFLSEL_POS)
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2025-03-19 15:59:12 +08:00
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/* UART_UARTIMSC_OFFSET @0x038 */
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#define UART_UARTIMSC_RIMIM (1 << 0U)
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#define UART_UARTIMSC_CTSMIM (1 << 1U)
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#define UART_UARTIMSC_DCDMIM (1 << 2U)
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#define UART_UARTIMSC_DSRMIM (1 << 3U)
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#define UART_UARTIMSC_RXIM (1 << 4U)
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#define UART_UARTIMSC_TXIM (1 << 5U)
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#define UART_UARTIMSC_RTIM (1 << 6U)
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#define UART_UARTIMSC_FEIM (1 << 7U)
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#define UART_UARTIMSC_PEIM (1 << 8U)
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#define UART_UARTIMSC_BEIM (1 << 9U)
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#define UART_UARTIMSC_OEIM (1 << 10U)
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/* UART_UARTRIS_OFFSET @0x03C */
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#define UART_UARTRIS_RIRMIS (1 << 0U)
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#define UART_UARTRIS_CTSRMIS (1 << 1U)
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#define UART_UARTRIS_DCDRMIS (1 << 2U)
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#define UART_UARTRIS_DSRRMIS (1 << 3U)
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#define UART_UARTRIS_RXRIS (1 << 4U)
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#define UART_UARTRIS_TXRIS (1 << 5U)
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#define UART_UARTRIS_RTRIS (1 << 6U)
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#define UART_UARTRIS_FERIS (1 << 7U)
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#define UART_UARTRIS_PERIS (1 << 8U)
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#define UART_UARTRIS_BERIS (1 << 9U)
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#define UART_UARTRIS_OERIS (1 << 10U)
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/* UART_UARTMIS_OFFSET @0x040 */
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#define UART_UARTMIS_RIMMIS (1 << 0U)
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#define UART_UARTMIS_CTSMMIS (1 << 1U)
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#define UART_UARTMIS_DCDMMIS (1 << 2U)
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#define UART_UARTMIS_DSRMMIS (1 << 3U)
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#define UART_UARTMIS_RXMIS (1 << 4U)
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#define UART_UARTMIS_TXMIS (1 << 5U)
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#define UART_UARTMIS_RTMIS (1 << 6U)
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#define UART_UARTMIS_FEMIS (1 << 7U)
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#define UART_UARTMIS_PEMIS (1 << 8U)
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#define UART_UARTMIS_BEMIS (1 << 9U)
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#define UART_UARTMIS_OEMIS (1 << 10U)
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/* UART_UARTICR_OFFSET @0x044 */
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#define UART_UARTICR_RIMIC (1 << 0U)
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#define UART_UARTICR_CTSMIC (1 << 1U)
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#define UART_UARTICR_DCDMIC (1 << 2U)
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#define UART_UARTICR_DSRMIC (1 << 3U)
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#define UART_UARTICR_RXIC (1 << 4U)
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#define UART_UARTICR_TXIC (1 << 5U)
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#define UART_UARTICR_RTIC (1 << 6U)
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#define UART_UARTICR_FEIC (1 << 7U)
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#define UART_UARTICR_PEIC (1 << 8U)
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#define UART_UARTICR_BEIC (1 << 9U)
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#define UART_UARTICR_OEIC (1 << 10U)
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/* UART_UARTDMACR_OFFSET @0x048 */
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#define UART_UARTDMACR_RXDMAE (1 << 0U)
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#define UART_UARTDMACR_TXDMAE (1 << 1U)
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#define UART_UARTDMACR_DMAONERR (1 << 2U)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __UART_REG_H__ */
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