2025-03-29 16:32:49 +08:00
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#ifndef __HARDWARE_UART_H__
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#define __HARDWARE_UART_H__
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2025-03-19 15:59:12 +08:00
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#include "reg.h"
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#include "uart_reg.h"
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#define UART_INT_RI (1 << 0U)
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#define UART_INT_CTS (1 << 1U)
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#define UART_INT_DCD (1 << 2U)
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#define UART_INT_DSR (1 << 3U)
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#define UART_INT_RX (1 << 4U)
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#define UART_INT_TX (1 << 5U)
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#define UART_INT_RTO (1 << 6U)
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#define UART_INT_FE (1 << 7U)
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#define UART_INT_PE (1 << 8U)
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#define UART_INT_BE (1 << 9U)
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#define UART_INT_OE (1 << 10U)
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#define UART_INT_ALL ((1 << 11U) - 1)
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#define UART_MODE_NONE (0)
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#define UART_MODE_TX_ONLY (1)
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#define UART_MODE_RX_ONLY (2)
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#define UART_MODE_TX_RX (3)
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2025-06-02 17:27:26 +08:00
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#define UART_DATABITS_5 (0 << UART_UARTLCR_H_WLEN_POS)
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#define UART_DATABITS_6 (1 << UART_UARTLCR_H_WLEN_POS)
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#define UART_DATABITS_7 (2 << UART_UARTLCR_H_WLEN_POS)
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#define UART_DATABITS_8 (3 << UART_UARTLCR_H_WLEN_POS)
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2025-03-19 15:59:12 +08:00
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#define UART_PARITY_NONE (0)
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2025-06-02 17:27:26 +08:00
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#define UART_PARITY_ODD (UART_UARTLCR_H_PEN)
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#define UART_PARITY_EVEN (UART_UARTLCR_H_PEN | UART_UARTLCR_H_EPS)
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#define UART_PARITY_MARK0 (UART_UARTLCR_H_PEN | UART_UARTLCR_H_SPS | UART_UARTLCR_H_EPS)
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#define UART_PARITY_MARK1 (UART_UARTLCR_H_PEN | UART_UARTLCR_H_SPS)
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2025-03-19 15:59:12 +08:00
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#define UART_STOPBITS_1 (0)
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2025-06-02 17:27:26 +08:00
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#define UART_STOPBITS_2 (UART_UARTLCR_H_STP2)
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2025-03-19 15:59:12 +08:00
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#define UART_FIFO_LEVEL_1_8 (0)
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#define UART_FIFO_LEVEL_1_4 (1)
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#define UART_FIFO_LEVEL_1_2 (2)
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#define UART_FIFO_LEVEL_3_4 (3)
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#define UART_FIFO_LEVEL_7_8 (4)
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#define UART_FLAG_CTS (1 << 0U)
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#define UART_FLAG_DSR (1 << 1U)
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#define UART_FLAG_DCD (1 << 2U)
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#define UART_FLAG_BUSY (1 << 3U)
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#define UART_FLAG_RXFE (1 << 4U)
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#define UART_FLAG_TXFF (1 << 5U)
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#define UART_FLAG_RXFF (1 << 6U)
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#define UART_FLAG_TXFE (1 << 7U)
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#define UART_FLAG_RI (1 << 8U)
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struct uart_cfg_s {
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2025-03-19 22:15:07 +08:00
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uint32_t baudrate;
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2025-03-19 15:59:12 +08:00
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uint8_t mode;
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uint8_t data_bits;
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uint8_t parity;
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uint8_t stop_bits;
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uint8_t fifo_enable;
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uint8_t tx_fifo_level;
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uint8_t rx_fifo_level;
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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2025-06-02 17:27:26 +08:00
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void uart_init(uart_hw_t *uart, uint32_t baudrate, uint32_t cfg);
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uint32_t uart_get_flags(uart_hw_t *uart);
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void uart_write_block(uart_hw_t *uart, uint8_t *data, uint32_t length);
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int uart_put_char(uart_hw_t *uart, uint8_t c);
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int uart_get_char(uart_hw_t *uart);
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2025-03-19 15:59:12 +08:00
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2025-06-02 17:27:26 +08:00
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uint32_t uart_int_get_raw_status(uart_hw_t *uart);
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uint32_t uart_int_get_status(uart_hw_t *uart);
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void uart_int_clear(uart_hw_t *uart, uint32_t int_type);
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void uart_int_enable(uart_hw_t *uart, uint32_t int_type);
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void uart_int_disable(uart_hw_t *uart, uint32_t int_type);
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uint32_t uart_int_get_mask_status(uart_hw_t *uart);
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2025-03-19 15:59:12 +08:00
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#ifdef __cplusplus
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}
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#endif
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2025-03-29 16:32:49 +08:00
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#endif /* __HARDWARE_UART_H__ */
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