126 lines
4.2 KiB
C
126 lines
4.2 KiB
C
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#ifndef __HARDWARE_CLOCK_REG_H__
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#define __HARDWARE_CLOCK_REG_H__
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/* ROSC_BASE @0x40060000 */
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#define CLOCK_ROSC_CTRL_OFFSET (0x000)
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#define CLOCK_ROSC_FREQA_OFFSET (0x004)
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#define CLOCK_ROSC_FREQB_OFFSET (0x008)
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#define CLOCK_ROSC_DORMANT_OFFSET (0x00C)
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#define CLOCK_ROSC_DIV_OFFSET (0x010)
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#define CLOCK_ROSC_PHASE_OFFSET (0x014)
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#define CLOCK_ROSC_STATUS_OFFSET (0x018)
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#define CLOCK_ROSC_RANDOMBIT_OFFSET (0x01C)
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#define CLOCK_ROSC_COUNT_OFFSET (0x020)
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/* XOSC_BASE @0x40024000 */
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#define CLOCK_XOSC_CTRL_OFFSET (0x000)
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#define CLOCK_XOSC_STATUS_OFFSET (0x004)
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#define CLOCK_XOSC_DORMANT_OFFSET (0x008)
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#define CLOCK_XOSC_STARTUP_OFFSET (0x00C)
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#define CLOCK_XOSC_COUNT_OFFSET (0x01C)
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/* PLL_SYS_BASE @0x40028000 */
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/* PLL_USB_BASE @0x4002C000 */
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#define CLOCK_PLL_CS_OFFSET (0x000)
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#define CLOCK_PLL_PWR_OFFSET (0x004)
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#define CLOCK_PLL_FBDIV_INT_OFFSET (0x008)
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#define CLOCK_PLL_PRIM_OFFSET (0x00C)
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/* CLOCKS_BASE @0x40008000 */
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#define CLOCK_CTRL_OFFSET (0x000)
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#define CLOCK_DIV_OFFSET (0x004)
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#define CLOCK_SELECTED_OFFSET (0x008)
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#define CLOCK_GPOUT0_CTRL_OFFSET (0x000)
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#define CLOCK_GPOUT0_DIV_OFFSET (0x004)
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#define CLOCK_GPOUT0_SELECTED_OFFSET (0x008)
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#define CLOCK_GPOUT1_CTRL_OFFSET (0x00C)
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#define CLOCK_GPOUT1_DIV_OFFSET (0x010)
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#define CLOCK_GPOUT1_SELECTED_OFFSET (0x014)
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#define CLOCK_GPOUT2_CTRL_OFFSET (0x018)
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#define CLOCK_GPOUT2_DIV_OFFSET (0x01C)
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#define CLOCK_GPOUT2_SELECTED_OFFSET (0x020)
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#define CLOCK_GPOUT3_CTRL_OFFSET (0x024)
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#define CLOCK_GPOUT3_DIV_OFFSET (0x028)
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#define CLOCK_GPOUT3_SELECTED_OFFSET (0x02C)
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#define CLOCK_REF_CTRL_OFFSET (0x030)
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#define CLOCK_REF_DIV_OFFSET (0x034)
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#define CLOCK_REF_SELECTED_OFFSET (0x038)
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#define CLOCK_SYS_CTRL_OFFSET (0x03C)
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#define CLOCK_SYS_DIV_OFFSET (0x040)
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#define CLOCK_SYS_SELECTED_OFFSET (0x044)
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#define CLOCK_PERI_CTRL_OFFSET (0x048)
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#define CLOCK_PERI_DIV_OFFSET (0x04C)
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#define CLOCK_PERI_SELECTED_OFFSET (0x050)
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#define CLOCK_USB_CTRL_OFFSET (0x054)
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#define CLOCK_USB_DIV_OFFSET (0x058)
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#define CLOCK_USB_SELECTED_OFFSET (0x05C)
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#define CLOCK_ADC_CTRL_OFFSET (0x060)
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#define CLOCK_ADC_DIV_OFFSET (0x064)
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#define CLOCK_ADC_SELECTED_OFFSET (0x068)
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#define CLOCK_RTC_CTRL_OFFSET (0x06C)
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#define CLOCK_RTC_DIV_OFFSET (0x070)
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#define CLOCK_RTC_SELECTED_OFFSET (0x074)
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/* CLOCK_ROSC_CTRL_OFFSET */
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#define CLOCK_ROSC_FREQ_RANGE_POS (0)
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#define CLOCK_ROSC_FREQ_RANGE_MASK (0xFFF)
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#define CLOCK_ROSC_ENABLE_POS (12)
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#define CLOCK_ROSC_ENABLE_MASK (0xFFF)
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/* CLOCK_ROSC_FREQ_OFFSET */
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#define CLOCK_ROSC_STRENGTH_MASK (0x7)
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/* CLOCK_XOSC_CTRL_OFFSET */
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#define CLOCK_XOSC_FREQ_RANGE_POS (0)
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#define CLOCK_XOSC_FREQ_RANGE_MASK (0xFFF)
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#define CLOCK_XOSC_ENABLE_POS (12)
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#define CLOCK_XOSC_ENABLE_MASK (0xFFF)
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/* CLOCK_XOSC_STARTUP_OFFSET */
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#define CLOCK_XOSC_STARTUP_DELAY_POS (0)
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#define CLOCK_XOSC_STARTUP_DELAY_MASK (0x3FFF)
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#define CLOCK_XOSC_STARTUP_X4_POS (20)
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/* CLOCK_PLL_CS_OFFSET */
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#define CLOCK_PLL_REFDIV_POS (0)
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#define CLOCK_PLL_REFDIV_MASK (0x3F)
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#define CLOCK_PLL_BYPASS_POS (8)
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#define CLOCK_PLL_LOCK_POS (31)
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/* CLOCK_PLL_PWR_OFFSET */
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#define CLOCK_PLL_PD_POS (0)
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#define CLOCK_PLL_DSMPD_POS (2)
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#define CLOCK_PLL_POSTDIVPD_POS (3)
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#define CLOCK_PLL_VCOPD_POS (5)
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#define CLOCK_PLL_PWR_MASK ((1 << CLOCK_PLL_PD_POS) | \
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(1 << CLOCK_PLL_DSMPD_POS) | \
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(1 << CLOCK_PLL_POSTDIVPD_POS) | \
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(1 << CLOCK_PLL_VCOPD_POS))
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/* CLOCK_PLL_PRIM_OFFSET */
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#define CLOCK_PLL_POSTDIV2_POS (12)
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#define CLOCK_PLL_POSTDIV2_MASK (0x7)
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#define CLOCK_PLL_POSTDIV1_POS (16)
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#define CLOCK_PLL_POSTDIV1_MASK (0x7)
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/* CLOCK_CTRL_OFFSET */
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#define CLOCK_SRC_POS (0)
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#define CLOCK_SRC_MASK (0x3)
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#define CLOCK_AUXSRC_POS (5)
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#define CLOCK_AUXSRC_MASK (0xF)
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#define CLOCK_KILL_POS (10)
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#define CLOCK_ENABLE_POS (11)
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#define CLOCK_DC50_POS (12)
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#define CLOCK_PHASE_POS (16)
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#define CLOCK_PHASE_MASK (0x3)
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#define CLOCK_NUDGE_POS (20)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HARDWARE_CLOCK_REG_H__ */
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