diff --git a/driver/inc/reg/gpio_reg.h b/driver/inc/reg/gpio_reg.h
index dcf61d7..381c25f 100644
--- a/driver/inc/reg/gpio_reg.h
+++ b/driver/inc/reg/gpio_reg.h
@@ -90,6 +90,61 @@
 #define GPIO_PADS_IE_POS         (6)
 #define GPIO_PADS_OD_POS         (7)
 
+typedef struct {
+    io_rw_32 voltage_select;
+    io_rw_32 io[30];
+} pads_bank0_hw_t;
+
+#define pads_bank0_hw       ((pads_bank0_hw_t *)PADS_BANK0_BASE)
+#define pads_bank0_hw_set   ((pads_bank0_hw_t *const)hw_set_alias_untyped(pads_bank0_hw))
+#define pads_bank0_hw_clear ((pads_bank0_hw_t *const)hw_clear_alias_untyped(pads_bank0_hw))
+
+typedef struct {
+    io_rw_32 voltage_select;
+    io_rw_32 io_qspi_sclk;
+    io_rw_32 io_qspi_sd0;
+    io_rw_32 io_qspi_sd1;
+    io_rw_32 io_qspi_sd2;
+    io_rw_32 io_qspi_sd3;
+    io_rw_32 io_qspi_ss;
+} pads_qspi_hw_t;
+
+#define pads_qspi_hw       ((pads_qspi_hw_t *const)PADS_QSPI_BASE)
+#define pads_qspi_hw_set   ((pads_qspi_hw_t *const)hw_set_alias_untyped(pads_qspi_hw))
+#define pads_qspi_hw_clear ((pads_qspi_hw_t *const)hw_clear_alias_untyped(pads_qspi_hw))
+
+typedef struct {
+    io_rw_32 inte[4];
+    io_rw_32 intf[4];
+    io_rw_32 ints[4];
+} io_irq_ctrl_hw_t;
+
+typedef struct {
+    struct {
+        io_rw_32 status;
+        io_rw_32 ctrl;
+    } io[30];
+    io_rw_32 intr[4];
+    io_irq_ctrl_hw_t proc0_irq_ctrl;
+    io_irq_ctrl_hw_t proc1_irq_ctrl;
+    io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
+} iobank0_hw_t;
+
+#define iobank0_hw       ((iobank0_hw_t *const)IO_BANK0_BASE)
+#define iobank0_hw_set   ((iobank0_hw_t *const)hw_set_alias_untyped(iobank0_hw))
+#define iobank0_hw_clear ((iobank0_hw_t *const)hw_clear_alias_untyped(iobank0_hw))
+
+typedef struct {
+    struct {
+        io_rw_32 status;
+        io_rw_32 ctrl;
+    } io[6];
+} ioqspi_hw_t;
+
+#define ioqspi_hw       ((ioqspi_hw_t *const)IO_QSPI_BASE)
+#define ioqspi_hw_set   ((ioqspi_hw_t *const)hw_set_alias_untyped(ioqspi_hw))
+#define ioqspi_hw_clear ((ioqspi_hw_t *const)hw_clear_alias_untyped(ioqspi_hw))
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/driver/inc/reg/ssi_reg.h b/driver/inc/reg/ssi_reg.h
index d649088..5307bd2 100644
--- a/driver/inc/reg/ssi_reg.h
+++ b/driver/inc/reg/ssi_reg.h
@@ -3,6 +3,38 @@
 
 #include "reg.h"
 
+#define SSI_CTRLR0_TMOD_POS                    (8U)
+#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX_MASK   (0x0 << SSI_CTRLR0_TMOD_POS)
+#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY_MASK     (0x1 << SSI_CTRLR0_TMOD_POS)
+#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY_MASK     (0x2 << SSI_CTRLR0_TMOD_POS)
+#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ_MASK (0x3 << SSI_CTRLR0_TMOD_POS)
+#define SSI_CTRLR0_DFS_32_POS                  (16U)
+#define SSI_CTRLR0_SPI_FRF_POS                 (21U)
+#define SSI_CTRLR0_SPI_FRF_VALUE_STD_MASK      (0x0 << SSI_CTRLR0_SPI_FRF_POS)
+#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL_MASK     (0x1 << SSI_CTRLR0_SPI_FRF_POS)
+#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD_MASK     (0x2 << SSI_CTRLR0_SPI_FRF_POS)
+
+#define SSI_SPI_CTRLR0_TRANS_TYPE_POS             (0U)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A_MASK (0x0 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A_MASK (0x1 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A_MASK (0x2 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
+#define SSI_SPI_CTRLR0_ADDR_L_POS                 (2U)
+#define SSI_SPI_CTRLR0_INST_L_POS                 (8U)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE_MASK     (0x0 << SSI_SPI_CTRLR0_INST_L_POS)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_4B_MASK       (0x1 << SSI_SPI_CTRLR0_INST_L_POS)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_8B_MASK       (0x2 << SSI_SPI_CTRLR0_INST_L_POS)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_16_MASKB      (0x3 << SSI_SPI_CTRLR0_INST_L_POS)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_POS            (11U)
+#define SSI_SPI_CTRLR0_XIP_CMD_POS                (24U)
+
+#define SSI_SR_BUSY (1 << 0)
+#define SSI_SR_TFNF (1 << 1)
+#define SSI_SR_TFE  (1 << 2)
+#define SSI_SR_RFNE (1 << 3)
+#define SSI_SR_RFF  (1 << 4)
+#define SSI_SR_TXE  (1 << 5)
+#define SSI_SR_DCOL (1 << 6)
+
 typedef struct {
     io_rw_32 ctrlr0;
     io_rw_32 ctrlr1;