From 823ef3ff28c82beebbe286e8bff37b33499e1069 Mon Sep 17 00:00:00 2001 From: zhji Date: Sun, 18 May 2025 22:09:57 +0800 Subject: [PATCH] [feat] add clock_xxx_get_freq function --- driver/inc/clock.h | 13 +- driver/inc/reg/clock_reg.h | 8 +- driver/inc/system.h | 10 +- driver/src/clock.c | 242 +++++++++++++++++++++++ driver/src/system.c | 112 ++--------- driver/src/uart.c | 3 +- example/boot2/main.c | 9 +- example/peripherals/dma/dma_sniff/main.c | 9 +- 8 files changed, 286 insertions(+), 120 deletions(-) diff --git a/driver/inc/clock.h b/driver/inc/clock.h index 018f6ec..c9f60e9 100644 --- a/driver/inc/clock.h +++ b/driver/inc/clock.h @@ -125,7 +125,7 @@ void clock_usbpll_init(uint8_t refdiv, uint16_t feedback, uint8_t postdiv1, uint void clock_syspll_deinit(void); void clock_usbpll_deinit(void); -/* clock function */ +/* clock set function */ void clock_gpout_set(uint8_t id, uint8_t enable, uint8_t src, uint32_t div); /* div is 1~16777215 */ void clock_ref_set(uint8_t src, uint32_t div); /* div is 1~3 */ void clock_sys_set(uint8_t src, uint32_t div); /* div is 1~16777215 */ @@ -134,6 +134,17 @@ void clock_usb_set(uint8_t enable, uint8_t src, uint32_t div); /* div is 1~3 */ void clock_adc_set(uint8_t enable, uint8_t src, uint32_t div); /* div is 1~3 */ void clock_rtc_set(uint8_t enable, uint8_t src, uint32_t div); /* div is 1~16777215 */ +/* clock get frequency function */ +uint32_t clock_syspll_get_freq(void); +uint32_t clock_usbpll_get_freq(void); +uint32_t clock_gpout_get_freq(uint8_t id); +uint32_t clock_ref_get_freq(void); +uint32_t clock_sys_get_freq(void); +uint32_t clock_peri_get_freq(void); +uint32_t clock_usb_get_freq(void); +uint32_t clock_adc_get_freq(void); +uint32_t clock_rtc_get_freq(void); + #ifdef __cplusplus } #endif diff --git a/driver/inc/reg/clock_reg.h b/driver/inc/reg/clock_reg.h index 578b419..975d7a4 100644 --- a/driver/inc/reg/clock_reg.h +++ b/driver/inc/reg/clock_reg.h @@ -101,7 +101,9 @@ /* CLOCK_CTRL_OFFSET @ 0x000 */ #define CLOCK_CTRL_SRC_POS (0U) +#define CLOCK_CTRL_SRC_MASK (0xF << CLOCK_CTRL_SRC_POS) #define CLOCK_CTRL_AUXSRC_POS (5U) +#define CLOCK_CTRL_AUXSRC_MASK (0xF << CLOCK_CTRL_AUXSRC_POS) #define CLOCK_CTRL_KILL (1 << 10U) #define CLOCK_CTRL_ENABLE (1 << 11U) #define CLOCK_CTRL_DC50 (1 << 12U) @@ -149,8 +151,6 @@ typedef struct { } clocks_hw_t; #define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) -#define clocks_hw_set ((clocks_hw *const)hw_set_alias_untyped(clocks_hw)) -#define clocks_hw_clear ((clocks_hw *const)hw_clear_alias_untyped(clocks_hw)) typedef struct { io_rw_32 cs; @@ -160,11 +160,7 @@ typedef struct { } pll_hw_t; #define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE) -#define pll_sys_hw_set ((pll_sys_hw *const)hw_set_alias_untyped(pll_sys_hw)) -#define pll_sys_hw_clear ((pll_sys_hw *const)hw_clear_alias_untyped(pll_sys_hw)) #define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE) -#define pll_usb_hw_set ((pll_usb_hw *const)hw_set_alias_untyped(pll_usb_hw)) -#define pll_usb_hw_clear ((pll_usb_hw *const)hw_clear_alias_untyped(pll_usb_hw)) typedef struct { io_rw_32 ctrl; diff --git a/driver/inc/system.h b/driver/inc/system.h index 0a54462..0de4af2 100644 --- a/driver/inc/system.h +++ b/driver/inc/system.h @@ -36,14 +36,6 @@ #define SYSTEM_BLOCK_PROC0 (1 << 15) #define SYSTEM_BLOCK_PROC1 (1 << 16) -#define SYSTEM_CLOCK_REF_XOSC_8MHZ (0) -#define SYSTEM_CLOCK_REF_XOSC_12MHZ (1) -#define SYSTEM_CLOCK_REF_XOSC_24MHZ (2) -#define SYSTEM_CLOCK_REF_XOSC_32MHZ (3) -#define SYSTEM_CLOCK_REF_XOSC_40MHZ (4) -#define SYSTEM_CLOCK_REF_XOSC_50MHZ (5) -#define SYSTEM_CLOCK_REF_XOSC_MHZ_COUNT (6) - #define SYSTEM_CLOCK_FREQ_48MHZ (0) #define SYSTEM_CLOCK_FREQ_96MHZ (1) #define SYSTEM_CLOCK_FREQ_100MHZ (2) @@ -74,7 +66,7 @@ void system_wdg_unbound(uint32_t block); uint8_t system_block_is_available(uint32_t block); void system_init(void); -void system_clock_config(uint8_t ref_xosc, uint8_t sys_freq); +void system_clock_config(uint8_t sys_freq); #ifdef __cplusplus } diff --git a/driver/src/clock.c b/driver/src/clock.c index b88359e..1b6e95c 100644 --- a/driver/src/clock.c +++ b/driver/src/clock.c @@ -335,6 +335,9 @@ void clock_gpout_set(uint8_t id, uint8_t enable, uint8_t src, uint32_t div) { uint32_t val; + if (id > 3) { + return; + } div = (div > 0xFFFFFF) ? 0xFFFFFF : div; div = div << CLOCK_DIV_INT_POS; val = ((uint32_t)src << CLOCK_CTRL_AUXSRC_POS) | CLOCK_CTRL_DC50; @@ -460,3 +463,242 @@ void clock_rtc_set(uint8_t enable, uint8_t src, uint32_t div) clocks_hw->clk[CLOCK_RTC].ctrl = val; } } + +static uint32_t clock_rosc_get_freq(void) +{ + return 6500000; /* ROSC runs at a nominal 6.5MHz */ +} + +static uint32_t clock_xosc_get_freq(void) +{ + return 12 * 1000 * 1000; /* 1MHz~15MHz is available, but 12MHz crystal is perfect */ +} + +static uint32_t clock_pll_get_freq(pll_hw_t *pll) +{ + uint32_t refdiv, feedback, postdiv; + + if (pll->pwr) { + return 0; + } + refdiv = (pll->cs & CLOCK_PLL_CS_REFDIV_MASK) >> CLOCK_PLL_CS_REFDIV_POS; + feedback = pll->fbdiv_int; + postdiv = pll->prim; + postdiv = ((postdiv & CLOCK_PLL_PRIM_POSTDIV1_MASK) >> CLOCK_PLL_PRIM_POSTDIV1_POS) \ + * ((postdiv & CLOCK_PLL_PRIM_POSTDIV2_MASK) >> CLOCK_PLL_PRIM_POSTDIV2_POS); + return (clock_xosc_get_freq() * feedback / (refdiv * postdiv)); +} + +uint32_t clock_syspll_get_freq(void) +{ + return clock_pll_get_freq(pll_sys_hw); +} + +uint32_t clock_usbpll_get_freq(void) +{ + return clock_pll_get_freq(pll_usb_hw); +} + +uint32_t clock_gpout_get_freq(uint8_t id) +{ + uint32_t ctrl, auxsrc, freq, div; + + if (id > 3) { + return 0; + } + ctrl = clocks_hw->clk[CLOCK_GPOUT0 + id].ctrl; + if ((ctrl & CLOCK_CTRL_ENABLE) == 0) { + return 0; + } + div = clocks_hw->clk[CLOCK_GPOUT0 + id].div >> CLOCK_DIV_INT_POS; + if (div == 0) { + div = 65536; + } + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_syspll_get_freq(); + } else if (auxsrc == 3) { + freq = clock_usbpll_get_freq(); + } else if (auxsrc == 4) { + freq = clock_rosc_get_freq(); + } else if (auxsrc == 5) { + freq = clock_xosc_get_freq(); + } else if (auxsrc == 6) { + freq = clock_sys_get_freq(); + } else if (auxsrc == 7) { + freq = clock_usb_get_freq(); + } else if (auxsrc == 8) { + freq = clock_adc_get_freq(); + } else if (auxsrc == 9) { + freq = clock_rtc_get_freq(); + } else if (auxsrc == 10) { + freq = clock_ref_get_freq(); + } else { + return 0; + } + return freq / div; +} + +uint32_t clock_ref_get_freq(void) +{ + uint32_t ctrl, src, auxsrc, freq, div; + + div = clocks_hw->clk[CLOCK_REF].div >> CLOCK_DIV_INT_POS; + if (div == 0) { + div = 65536; + } + ctrl = clocks_hw->clk[CLOCK_REF].ctrl; + src = (ctrl & CLOCK_CTRL_SRC_MASK) >> CLOCK_CTRL_SRC_POS; + if (src == 0) { + freq = clock_rosc_get_freq(); + } else if (src == 2) { + freq = clock_xosc_get_freq(); + } else if (src == 1) { + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_usbpll_get_freq(); + } else { + return 0; + } + } else { + return 0; + } + return freq / div; +} + +uint32_t clock_sys_get_freq(void) +{ + uint32_t ctrl, src, auxsrc, freq, div; + + div = clocks_hw->clk[CLOCK_SYS].div >> CLOCK_DIV_INT_POS; + if (div == 0) { + div = 65536; + } + ctrl = clocks_hw->clk[CLOCK_SYS].ctrl; + src = (ctrl & CLOCK_CTRL_SRC_MASK) >> CLOCK_CTRL_SRC_POS; + if (src == 0) { + freq = clock_ref_get_freq(); + } else if (src == 1) { + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_syspll_get_freq(); + } else if (auxsrc == 1) { + freq = clock_usbpll_get_freq(); + } else if (auxsrc == 2) { + freq = clock_rosc_get_freq(); + } else if (auxsrc == 3) { + freq = clock_xosc_get_freq(); + } else { + return 0; + } + } else { + return 0; + } + return freq / div; +} + +uint32_t clock_peri_get_freq(void) +{ + uint32_t ctrl, auxsrc, freq; + + if ((clocks_hw->clk[CLOCK_PERI].ctrl & CLOCK_CTRL_ENABLE) == 0) { + return 0; + } + ctrl = clocks_hw->clk[CLOCK_PERI].ctrl; + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_sys_get_freq(); + } else if (auxsrc == 1) { + freq = clock_syspll_get_freq(); + } else if (auxsrc == 2) { + freq = clock_usbpll_get_freq(); + } else if (auxsrc == 3) { + freq = clock_rosc_get_freq(); + } else if (auxsrc == 4) { + freq = clock_xosc_get_freq(); + } else { + return 0; + } + return freq; +} + +uint32_t clock_usb_get_freq(void) +{ + uint32_t ctrl, auxsrc, freq, div; + + ctrl = clocks_hw->clk[CLOCK_USB].ctrl; + if ((ctrl & CLOCK_CTRL_ENABLE) == 0) { + return 0; + } + div = clocks_hw->clk[CLOCK_USB].div >> CLOCK_DIV_INT_POS; + if (div == 0) { + div = 65536; + } + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_usbpll_get_freq(); + } else if (auxsrc == 1) { + freq = clock_syspll_get_freq(); + } else if (auxsrc == 2) { + freq = clock_rosc_get_freq(); + } else if (auxsrc == 3) { + freq = clock_xosc_get_freq(); + } else { + return 0; + } + return freq / div; +} + +uint32_t clock_adc_get_freq(void) +{ + uint32_t ctrl, auxsrc, freq, div; + + ctrl = clocks_hw->clk[CLOCK_ADC].ctrl; + if ((ctrl & CLOCK_CTRL_ENABLE) == 0) { + return 0; + } + div = clocks_hw->clk[CLOCK_ADC].div >> CLOCK_DIV_INT_POS; + if (div == 0) { + div = 65536; + } + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_usbpll_get_freq(); + } else if (auxsrc == 1) { + freq = clock_syspll_get_freq(); + } else if (auxsrc == 2) { + freq = clock_rosc_get_freq(); + } else if (auxsrc == 3) { + freq = clock_xosc_get_freq(); + } else { + return 0; + } + return freq / div; +} + +uint32_t clock_rtc_get_freq(void) +{ + uint32_t ctrl, auxsrc, freq, div; + + ctrl = clocks_hw->clk[CLOCK_RTC].ctrl; + if ((ctrl & CLOCK_CTRL_ENABLE) == 0) { + return 0; + } + div = clocks_hw->clk[CLOCK_RTC].div >> CLOCK_DIV_INT_POS; + if (div == 0) { + div = 65536; + } + auxsrc = (ctrl & CLOCK_CTRL_AUXSRC_MASK) >> CLOCK_CTRL_AUXSRC_POS; + if (auxsrc == 0) { + freq = clock_usbpll_get_freq(); + } else if (auxsrc == 1) { + freq = clock_syspll_get_freq(); + } else if (auxsrc == 2) { + freq = clock_rosc_get_freq(); + } else if (auxsrc == 3) { + freq = clock_xosc_get_freq(); + } else { + return 0; + } + return freq / div; +} \ No newline at end of file diff --git a/driver/src/system.c b/driver/src/system.c index 8aae13d..0a305fa 100644 --- a/driver/src/system.c +++ b/driver/src/system.c @@ -122,102 +122,32 @@ void system_init(void) printf("system clock = 200MHz\r\n"); } -const static uint8_t system_clock_cfg_para[SYSTEM_CLOCK_REF_XOSC_MHZ_COUNT][SYSTEM_CLOCK_FREQ_MHZ_COUNT][5] = { - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_48MHZ] = {1, 2, 3, 4, 5}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_96MHZ] = {6, 7, 8, 9, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_100MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_120MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_125MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_144MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_150MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_192MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_200MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_240MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_250MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_320MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_384MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_8MHZ][SYSTEM_CLOCK_FREQ_400MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_48MHZ] = {1, 96, 6, 4, 1}, /* 12MHz / 1 * 96 / 6 / 4 = 48MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_96MHZ] = {1, 96, 6, 2, 1}, /* 12MHz / 1 * 96 / 6 / 2 = 96MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_100MHZ] = {1, 100, 6, 2, 1}, /* 12MHz / 1 * 100 / 6 / 2 = 100MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_120MHZ] = {1, 100, 5, 2, 1}, /* 12MHz / 1 * 100 / 5 / 2 = 120MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_125MHZ] = {1, 125, 6, 2, 1}, /* 12MHz / 1 * 125 / 6 / 2 = 125MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_144MHZ] = {1, 96, 4, 2, 1}, /* 12MHz / 1 * 96 / 4 / 2 = 144MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_150MHZ] = {1, 100, 4, 2, 1}, /* 12MHz / 1 * 100 / 4 / 2 = 150MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_192MHZ] = {1, 96, 6, 1, 1}, /* 12MHz / 1 * 96 / 6 / 1 = 192MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_200MHZ] = {1, 100, 6, 1, 1}, /* 12MHz / 1 * 100 / 6 / 1 = 200MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_240MHZ] = {1, 100, 5, 1, 1}, /* 12MHz / 1 * 100 / 5 / 1 = 240MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_250MHZ] = {1, 125, 6, 1, 1}, /* 12MHz / 1 * 125 / 6 / 1 = 250MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_320MHZ] = {1, 80, 3, 1, 1}, /* 12MHz / 1 * 80 / 3 / 1 = 320MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_384MHZ] = {1, 96, 3, 1, 1}, /* 12MHz / 1 * 96 / 3 / 1 = 384MHz */ - [SYSTEM_CLOCK_REF_XOSC_12MHZ][SYSTEM_CLOCK_FREQ_400MHZ] = {1, 100, 3, 1, 1}, /* 12MHz / 1 * 100 / 3 / 1 = 400MHz */ - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_48MHZ] = {1, 2, 3, 4, 5}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_96MHZ] = {6, 7, 8, 9, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_100MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_120MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_125MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_144MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_150MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_192MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_200MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_240MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_250MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_320MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_384MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_24MHZ][SYSTEM_CLOCK_FREQ_400MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_48MHZ] = {1, 2, 3, 4, 5}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_96MHZ] = {6, 7, 8, 9, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_100MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_120MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_125MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_144MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_150MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_192MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_200MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_240MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_250MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_320MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_384MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_32MHZ][SYSTEM_CLOCK_FREQ_400MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_48MHZ] = {1, 2, 3, 4, 5}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_96MHZ] = {6, 7, 8, 9, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_100MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_120MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_125MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_144MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_150MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_192MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_200MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_240MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_250MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_320MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_384MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_40MHZ][SYSTEM_CLOCK_FREQ_400MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_48MHZ] = {1, 2, 3, 4, 5}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_96MHZ] = {6, 7, 8, 9, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_100MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_120MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_125MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_144MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_150MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_192MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_200MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_240MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_250MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_384MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_320MHZ] = {0, 0, 0, 0, 0}, - [SYSTEM_CLOCK_REF_XOSC_50MHZ][SYSTEM_CLOCK_FREQ_400MHZ] = {0, 0, 0, 0, 0}, +const static uint8_t system_clock_cfg_para[SYSTEM_CLOCK_FREQ_MHZ_COUNT][5] = { + [SYSTEM_CLOCK_FREQ_48MHZ] = {1, 96, 6, 4, 1}, /* 12MHz / 1 * 96 / 6 / 4 = 48MHz */ + [SYSTEM_CLOCK_FREQ_96MHZ] = {1, 96, 6, 2, 1}, /* 12MHz / 1 * 96 / 6 / 2 = 96MHz */ + [SYSTEM_CLOCK_FREQ_100MHZ] = {1, 100, 6, 2, 1}, /* 12MHz / 1 * 100 / 6 / 2 = 100MHz */ + [SYSTEM_CLOCK_FREQ_120MHZ] = {1, 100, 5, 2, 1}, /* 12MHz / 1 * 100 / 5 / 2 = 120MHz */ + [SYSTEM_CLOCK_FREQ_125MHZ] = {1, 125, 6, 2, 1}, /* 12MHz / 1 * 125 / 6 / 2 = 125MHz */ + [SYSTEM_CLOCK_FREQ_144MHZ] = {1, 96, 4, 2, 1}, /* 12MHz / 1 * 96 / 4 / 2 = 144MHz */ + [SYSTEM_CLOCK_FREQ_150MHZ] = {1, 100, 4, 2, 1}, /* 12MHz / 1 * 100 / 4 / 2 = 150MHz */ + [SYSTEM_CLOCK_FREQ_192MHZ] = {1, 96, 6, 1, 1}, /* 12MHz / 1 * 96 / 6 / 1 = 192MHz */ + [SYSTEM_CLOCK_FREQ_200MHZ] = {1, 100, 6, 1, 1}, /* 12MHz / 1 * 100 / 6 / 1 = 200MHz */ + [SYSTEM_CLOCK_FREQ_240MHZ] = {1, 100, 5, 1, 1}, /* 12MHz / 1 * 100 / 5 / 1 = 240MHz */ + [SYSTEM_CLOCK_FREQ_250MHZ] = {1, 125, 6, 1, 1}, /* 12MHz / 1 * 125 / 6 / 1 = 250MHz */ + [SYSTEM_CLOCK_FREQ_320MHZ] = {1, 80, 3, 1, 1}, /* 12MHz / 1 * 80 / 3 / 1 = 320MHz */ + [SYSTEM_CLOCK_FREQ_384MHZ] = {1, 96, 3, 1, 1}, /* 12MHz / 1 * 96 / 3 / 1 = 384MHz */ + [SYSTEM_CLOCK_FREQ_400MHZ] = {1, 100, 3, 1, 1}, /* 12MHz / 1 * 100 / 3 / 1 = 400MHz */ }; -void system_clock_config(uint8_t ref_xosc, uint8_t sys_freq) +void system_clock_config(uint8_t sys_freq) { system_regulator_set(SYSTEM_REGULATOR_VOLTAGE_1P30V); clock_ref_set(CLOCK_REF_SRC_XOSC_GLITCHLESS, 1); clock_sys_set(CLOCK_SYS_SRC_REF_GLITCHLESS, 1); - clock_syspll_init(system_clock_cfg_para[ref_xosc][sys_freq][0], \ - system_clock_cfg_para[ref_xosc][sys_freq][1], \ - system_clock_cfg_para[ref_xosc][sys_freq][2], \ - system_clock_cfg_para[ref_xosc][sys_freq][3]); - clock_sys_set(CLOCK_SYS_SRC_SYSPLL, system_clock_cfg_para[ref_xosc][sys_freq][4]); + clock_syspll_init(system_clock_cfg_para[sys_freq][0], \ + system_clock_cfg_para[sys_freq][1], \ + system_clock_cfg_para[sys_freq][2], \ + system_clock_cfg_para[sys_freq][3]); + clock_sys_set(CLOCK_SYS_SRC_SYSPLL, system_clock_cfg_para[sys_freq][4]); clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL); } diff --git a/driver/src/uart.c b/driver/src/uart.c index 4a2543a..8b412d9 100644 --- a/driver/src/uart.c +++ b/driver/src/uart.c @@ -1,10 +1,11 @@ #include "uart.h" +#include "clock.h" void uart_init(uint8_t uart_id, struct uart_cfg_s *cfg) { uint32_t addr, val; - uart_set_baudrate(uart_id, 200 * 1000 * 1000, cfg->baudrate); + uart_set_baudrate(uart_id, clock_peri_get_freq(), cfg->baudrate); addr = UART0_BASE + UART_UARTLCR_H_OFFSET + (UART1_BASE - UART0_BASE) * uart_id; val = getreg32(addr); diff --git a/example/boot2/main.c b/example/boot2/main.c index 8b493c1..7014d33 100644 --- a/example/boot2/main.c +++ b/example/boot2/main.c @@ -1,5 +1,6 @@ #include "gpio.h" #include "ssi_reg.h" +#include "system.h" void __attribute__((section(".text.boot2_pre"))) boot2_copy_self(void) { @@ -219,13 +220,7 @@ int main(void) { uint32_t boot_pin_low, boot_pin_high; - clock_ref_set_src(CLOCK_REF_SRC_XOSC_GLITCHLESS); - clock_sys_set_src(CLOCK_SYS_SRC_REF_GLITCHLESS); - /* refdiv >= 5MHz, VCO=[750:1600]MHz, fbdiv=[16:320], postdiv=[1:7] */ - clock_pll_init(CLOCK_PLL_SYSPLL, 1, 100, 5, 2); /* 12MHz / 1 * 100 / 5 / 2 = 120MHz */ - clock_sys_set_div(2 << 8); /* 120MHz / 2 = 60MHz */ - clock_sys_set_src(CLOCK_SYS_SRC_SYSPLL); - clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL); + system_clock_config(SYSTEM_CLOCK_FREQ_120MHZ); reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER); gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE); diff --git a/example/peripherals/dma/dma_sniff/main.c b/example/peripherals/dma/dma_sniff/main.c index 428a1e9..93df34a 100644 --- a/example/peripherals/dma/dma_sniff/main.c +++ b/example/peripherals/dma/dma_sniff/main.c @@ -1,4 +1,4 @@ -#include "reset.h" +#include "resets.h" #include "dma.h" #include "gpio.h" #include "uart.h" @@ -33,7 +33,7 @@ struct dma_sniff_cfg_s sniff_cfg = { }; struct uart_cfg_s uart_cfg = { - .baudrate = 6 * 1000 * 1000, + .baudrate = 2 * 1000 * 1000, .mode = UART_MODE_TX_RX, .data_bits = UART_DATABITS_8, .parity = UART_PARITY_NONE, @@ -47,8 +47,7 @@ int main(void) { uint32_t sniff_result; - reset_enable(RESET_DMA); - reset_disable(RESET_DMA); + reset_unreset_blocks_wait(RESETS_BLOCK_DMA); gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE); uart_init(UART_ID_0, &uart_cfg); @@ -75,7 +74,7 @@ int main(void) printf("CRC32 check succeed, result = 0x%08lX\r\n", sniff_result); } - __enable_irq(); + // __enable_irq(); while (1) {