From 8fb032ebb5b60fb1282ed595ac01ad0006b06410 Mon Sep 17 00:00:00 2001
From: zhji <jzhgonha@163.com>
Date: Mon, 21 Apr 2025 21:34:34 +0800
Subject: [PATCH] [feat] add init for boot2

---
 example/boot2/boot2_pre.S | 15 ++++++++++++++
 example/boot2/main.c      | 42 +++++++++++++++++++++++++++++++++++++++
 example/boot2/src/flash.c |  7 +++++--
 example/boot2/src/flash.h |  2 +-
 4 files changed, 63 insertions(+), 3 deletions(-)

diff --git a/example/boot2/boot2_pre.S b/example/boot2/boot2_pre.S
index a1cb425..02b42f4 100644
--- a/example/boot2/boot2_pre.S
+++ b/example/boot2/boot2_pre.S
@@ -7,6 +7,21 @@
 .section  .text.boot2_pre
 .type  boot2_pre, %function
 boot2_pre:
+    cpsid i
+
+/* clear bss section */
+    ldr r0, =0
+    ldr r1, =_bss_start
+    ldr r2, =_bss_end
+    cmp r1, r2
+    bhs 2f
+1:
+    str r0, [r1]
+    adds r1, r1, #4
+    cmp r1, r2
+    blo 1b
+2:
+
     ldr r0, =_stack_top
     msr msp, r0
     bl boot2_copy_self
diff --git a/example/boot2/main.c b/example/boot2/main.c
index 9d367ae..15e81ad 100644
--- a/example/boot2/main.c
+++ b/example/boot2/main.c
@@ -53,7 +53,49 @@ void __attribute__((section(".text.boot2_pre"))) boot2_copy_self(void)
     *reg = GPIO_OVER_OUT_FORCE_HIGH << GPIO_OVER_OUT_POS;
 }
 
+#include "resets.h"
+#include "clock.h"
+#include "uart.h"
+#include "flash.h"
+#include "timer.h"
+#include "stdio.h"
+
+uint8_t uart_tx_buffer[512];
+uint8_t uart_rx_buffer[512];
+uint8_t flash_tx_buffer[512];
+uint8_t flash_rx_buffer[512];
+
+struct uart_cfg_s uart_cfg = {
+    .baudrate = 2 * 1000 * 1000,
+    .mode = UART_MODE_TX_RX,
+    .data_bits = UART_DATABITS_8,
+    .parity = UART_PARITY_NONE,
+    .stop_bits = UART_STOPBITS_1,
+    .fifo_enable = ENABLE,
+    .tx_fifo_level = UART_FIFO_LEVEL_1_2,
+    .rx_fifo_level = UART_FIFO_LEVEL_1_2,
+};
+
 int main(void)
 {
+    clock_ref_set_src(CLOCK_REF_SRC_XOSC_GLITCHLESS);
+    clock_sys_set_src(CLOCK_SYS_SRC_REF_GLITCHLESS);
+    /* refdiv >= 5MHz, VCO=[750:1600]MHz, fbdiv=[16:320], postdiv=[1:7] */
+    clock_pll_init(CLOCK_PLL_SYSPLL, 1, 100, 5, 2); /* 12MHz / 1 * 100 / 5 / 2 = 120MHz */
+    clock_sys_set_div(2 << 8);                      /* 120MHz / 2 = 60MHz */
+    clock_sys_set_src(CLOCK_SYS_SRC_SYSPLL);
+    clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL);
+
+    reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER);
+    uart_init(UART_ID_0, &uart_cfg);
+    gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE);
+    timer_start();
+
+    printf("boot2 system clock = 60MHz\r\n");
+    printf("boot2 peripheral clock = 120MHz\r\n");
+
+    // flash_erase(addr);
+    flash_read(0x1200, flash_rx_buffer, FLASH_WRITE_SIZE);
+    // flash_write(addr, data, FLASH_WRITE_SIZE);
     return 0;
 }
diff --git a/example/boot2/src/flash.c b/example/boot2/src/flash.c
index 842830c..8b00696 100644
--- a/example/boot2/src/flash.c
+++ b/example/boot2/src/flash.c
@@ -83,11 +83,14 @@ void flash_erase(uint32_t addr)
     flash_wait_ready();
 }
 
-void flash_write(uint32_t addr, uint8_t *data)
+void flash_write(uint32_t addr, uint8_t *data, uint32_t length)
 {
+    if (length > FLASH_WRITE_SIZE) {
+        return;
+    }
     flash_enable_write();
     flash_put_cmd_addr(FLASHCMD_PAGE_PROGRAM, addr);
-    flash_put_get(data, (void *)0, FLASH_WRITE_SIZE, 4);
+    flash_put_get(data, (void *)0, length, 4);
     flash_wait_ready();
 }
 
diff --git a/example/boot2/src/flash.h b/example/boot2/src/flash.h
index 553ca64..769c127 100644
--- a/example/boot2/src/flash.h
+++ b/example/boot2/src/flash.h
@@ -19,7 +19,7 @@ extern "C" {
 #endif
 
 void flash_erase(uint32_t addr);
-void flash_write(uint32_t addr, uint8_t *data);
+void flash_write(uint32_t addr, uint8_t *data, uint32_t length);
 void flash_read(uint32_t addr, uint8_t *data, uint32_t length);
 
 #ifdef __cplusplus