[feat] add init for boot2
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a74fcfcf21
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8fb032ebb5
@ -7,6 +7,21 @@
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.section .text.boot2_pre
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.type boot2_pre, %function
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boot2_pre:
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cpsid i
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/* clear bss section */
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ldr r0, =0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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cmp r1, r2
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bhs 2f
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1:
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str r0, [r1]
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adds r1, r1, #4
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cmp r1, r2
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blo 1b
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2:
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ldr r0, =_stack_top
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msr msp, r0
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bl boot2_copy_self
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@ -53,7 +53,49 @@ void __attribute__((section(".text.boot2_pre"))) boot2_copy_self(void)
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*reg = GPIO_OVER_OUT_FORCE_HIGH << GPIO_OVER_OUT_POS;
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}
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#include "resets.h"
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#include "clock.h"
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#include "uart.h"
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#include "flash.h"
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#include "timer.h"
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#include "stdio.h"
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uint8_t uart_tx_buffer[512];
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uint8_t uart_rx_buffer[512];
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uint8_t flash_tx_buffer[512];
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uint8_t flash_rx_buffer[512];
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struct uart_cfg_s uart_cfg = {
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.baudrate = 2 * 1000 * 1000,
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.mode = UART_MODE_TX_RX,
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.data_bits = UART_DATABITS_8,
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.parity = UART_PARITY_NONE,
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.stop_bits = UART_STOPBITS_1,
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.fifo_enable = ENABLE,
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.tx_fifo_level = UART_FIFO_LEVEL_1_2,
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.rx_fifo_level = UART_FIFO_LEVEL_1_2,
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};
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int main(void)
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{
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clock_ref_set_src(CLOCK_REF_SRC_XOSC_GLITCHLESS);
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clock_sys_set_src(CLOCK_SYS_SRC_REF_GLITCHLESS);
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/* refdiv >= 5MHz, VCO=[750:1600]MHz, fbdiv=[16:320], postdiv=[1:7] */
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clock_pll_init(CLOCK_PLL_SYSPLL, 1, 100, 5, 2); /* 12MHz / 1 * 100 / 5 / 2 = 120MHz */
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clock_sys_set_div(2 << 8); /* 120MHz / 2 = 60MHz */
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clock_sys_set_src(CLOCK_SYS_SRC_SYSPLL);
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clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL);
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reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER);
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uart_init(UART_ID_0, &uart_cfg);
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gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE);
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timer_start();
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printf("boot2 system clock = 60MHz\r\n");
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printf("boot2 peripheral clock = 120MHz\r\n");
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// flash_erase(addr);
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flash_read(0x1200, flash_rx_buffer, FLASH_WRITE_SIZE);
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// flash_write(addr, data, FLASH_WRITE_SIZE);
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return 0;
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}
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@ -83,11 +83,14 @@ void flash_erase(uint32_t addr)
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flash_wait_ready();
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}
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void flash_write(uint32_t addr, uint8_t *data)
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void flash_write(uint32_t addr, uint8_t *data, uint32_t length)
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{
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if (length > FLASH_WRITE_SIZE) {
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return;
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}
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flash_enable_write();
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flash_put_cmd_addr(FLASHCMD_PAGE_PROGRAM, addr);
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flash_put_get(data, (void *)0, FLASH_WRITE_SIZE, 4);
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flash_put_get(data, (void *)0, length, 4);
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flash_wait_ready();
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}
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@ -19,7 +19,7 @@ extern "C" {
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#endif
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void flash_erase(uint32_t addr);
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void flash_write(uint32_t addr, uint8_t *data);
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void flash_write(uint32_t addr, uint8_t *data, uint32_t length);
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void flash_read(uint32_t addr, uint8_t *data, uint32_t length);
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#ifdef __cplusplus
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