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[update] update uart driver

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This commit is contained in:
zhji 2025-06-02 17:27:26 +08:00
parent 3771df2093
commit 96d31a0df1
12 changed files with 132 additions and 259 deletions
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4
component/printf/printf.c
View File

@ -3,8 +3,8 @@
#include "string.h"
#include "uart.h"
uint8_t console = UART_ID_0;
extern void uart_write_block(uint8_t uart_id, uint8_t *data, uint32_t length);
uart_hw_t *console = uart0_hw;
extern void uart_write_block(uart_hw_t *uart, uint8_t *data, uint32_t length);
int putchar(int c)
{

4
component/printf/vsnprintf.c
View File

@ -219,11 +219,11 @@ static inline void out_buffer(char character, void* buffer, size_t idx, size_t m
}
}
extern uint8_t console;
extern uart_hw_t *console;
static inline void out_console(char character, void* buffer, size_t idx, size_t maxlen)
{
while (uart_get_flags(console) & UART_FLAG_TXFF);
*(volatile uint8_t *)(UART0_BASE + UART_UARTDR_OFFSET) = (uint8_t)character;
console->dr = (uint8_t)character;
}

23
driver/inc/reg/uart_reg.h
View File

@ -1,29 +1,6 @@
#ifndef __HARDWARE_UART_REG_H__
#define __HARDWARE_UART_REG_H__
#define UART_UARTDR_OFFSET (0x000)
#define UART_UARTRSR_OFFSET (0x004)
#define UART_UARTFR_OFFSET (0x018)
#define UART_UARTILPR_OFFSET (0x020)
#define UART_UARTIBRD_OFFSET (0x024)
#define UART_UARTFBRD_OFFSET (0x028)
#define UART_UARTLCR_H_OFFSET (0x02C)
#define UART_UARTCR_OFFSET (0x030)
#define UART_UARTIFLS_OFFSET (0x034)
#define UART_UARTIMSC_OFFSET (0x038)
#define UART_UARTRIS_OFFSET (0x03C)
#define UART_UARTMIS_OFFSET (0x040)
#define UART_UARTICR_OFFSET (0x044)
#define UART_UARTDMACR_OFFSET (0x048)
#define UART_UARTPERIPHID0_OFFSET (0xFE0)
#define UART_UARTPERIPHID1_OFFSET (0xFE4)
#define UART_UARTPERIPHID2_OFFSET (0xFE8)
#define UART_UARTPERIPHID3_OFFSET (0xFEC)
#define UART_UARTPCELLID0 (0xFF0)
#define UART_UARTPCELLID1 (0xFF4)
#define UART_UARTPCELLID2 (0xFF8)
#define UART_UARTPCELLID3 (0xFFC)
/* UART_UARTDR_OFFSET @0x000 */
#define UART_UARTDR_DATA_POS (0U)
#define UART_UARTDR_DATA_MASK (0xFF << UART_UARTDR_DATA_POS)

44
driver/inc/uart.h
View File

@ -4,9 +4,6 @@
#include "reg.h"
#include "uart_reg.h"
#define UART_ID_0 (0)
#define UART_ID_1 (1)
#define UART_INT_RI (1 << 0U)
#define UART_INT_CTS (1 << 1U)
#define UART_INT_DCD (1 << 2U)
@ -25,19 +22,19 @@
#define UART_MODE_RX_ONLY (2)
#define UART_MODE_TX_RX (3)
#define UART_DATABITS_5 (0)
#define UART_DATABITS_6 (1)
#define UART_DATABITS_7 (2)
#define UART_DATABITS_8 (3)
#define UART_DATABITS_5 (0 << UART_UARTLCR_H_WLEN_POS)
#define UART_DATABITS_6 (1 << UART_UARTLCR_H_WLEN_POS)
#define UART_DATABITS_7 (2 << UART_UARTLCR_H_WLEN_POS)
#define UART_DATABITS_8 (3 << UART_UARTLCR_H_WLEN_POS)
#define UART_PARITY_NONE (0)
#define UART_PARITY_ODD (1)
#define UART_PARITY_EVEN (2)
#define UART_PARITY_MARK0 (3)
#define UART_PARITY_MARK1 (4)
#define UART_PARITY_ODD (UART_UARTLCR_H_PEN)
#define UART_PARITY_EVEN (UART_UARTLCR_H_PEN | UART_UARTLCR_H_EPS)
#define UART_PARITY_MARK0 (UART_UARTLCR_H_PEN | UART_UARTLCR_H_SPS | UART_UARTLCR_H_EPS)
#define UART_PARITY_MARK1 (UART_UARTLCR_H_PEN | UART_UARTLCR_H_SPS)
#define UART_STOPBITS_1 (0)
#define UART_STOPBITS_2 (1)
#define UART_STOPBITS_2 (UART_UARTLCR_H_STP2)
#define UART_FIFO_LEVEL_1_8 (0)
#define UART_FIFO_LEVEL_1_4 (1)
@ -70,19 +67,18 @@ struct uart_cfg_s {
extern "C" {
#endif
void uart_init(uint8_t uart_id, struct uart_cfg_s *cfg);
void uart_set_baudrate(uint8_t uart_id, uint32_t src_clk, uint32_t baudrate);
uint32_t uart_get_flags(uint8_t uart_id);
void uart_write_block(uint8_t uart_id, uint8_t *data, uint32_t length);
int uart_put_char(uint8_t uart_id, uint8_t c);
int uart_get_char(uint8_t uart_id);
void uart_init(uart_hw_t *uart, uint32_t baudrate, uint32_t cfg);
uint32_t uart_get_flags(uart_hw_t *uart);
void uart_write_block(uart_hw_t *uart, uint8_t *data, uint32_t length);
int uart_put_char(uart_hw_t *uart, uint8_t c);
int uart_get_char(uart_hw_t *uart);
uint32_t uart_int_get_raw_status(uint8_t uart_id);
uint32_t uart_int_get_status(uint8_t uart_id);
void uart_int_clear(uint8_t uart_id, uint32_t int_type);
void uart_int_enable(uint8_t uart_id, uint32_t int_type);
void uart_int_disable(uint8_t uart_id, uint32_t int_type);
uint32_t uart_int_get_mask_status(uint8_t uart_id);
uint32_t uart_int_get_raw_status(uart_hw_t *uart);
uint32_t uart_int_get_status(uart_hw_t *uart);
void uart_int_clear(uart_hw_t *uart, uint32_t int_type);
void uart_int_enable(uart_hw_t *uart, uint32_t int_type);
void uart_int_disable(uart_hw_t *uart, uint32_t int_type);
uint32_t uart_int_get_mask_status(uart_hw_t *uart);
#ifdef __cplusplus
}

13
driver/src/system.c
View File

@ -95,17 +95,6 @@ uint8_t system_block_is_available(uint32_t block)
void system_init(void)
{
struct uart_cfg_s uart_cfg = {
.baudrate = 6 * 1000 * 1000,
.mode = UART_MODE_TX_RX,
.data_bits = UART_DATABITS_8,
.parity = UART_PARITY_NONE,
.stop_bits = UART_STOPBITS_1,
.fifo_enable = ENABLE,
.tx_fifo_level = UART_FIFO_LEVEL_1_2,
.rx_fifo_level = UART_FIFO_LEVEL_1_2,
};
system_regulator_set(SYSTEM_REGULATOR_VOLTAGE_1P30V);
clock_ref_set(CLOCK_REF_SRC_XOSC_GLITCHLESS, 1);
clock_sys_set(CLOCK_SYS_SRC_REF_GLITCHLESS, 1);
@ -114,7 +103,7 @@ void system_init(void)
clock_sys_set(CLOCK_SYS_SRC_SYSPLL, 1); /* 200MHz / 1 = 200MHz */
clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL);
reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER);
uart_init(UART_ID_0, &uart_cfg);
uart_init(uart0_hw, 750 * 1000, UART_DATABITS_8 | UART_PARITY_NONE | UART_STOPBITS_1);
gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA);
timer_start();
irq_init();

195
driver/src/uart.c
View File

@ -1,93 +1,9 @@
#include "uart.h"
#include "clock.h"
#include "resets.h"
void uart_init(uint8_t uart_id, struct uart_cfg_s *cfg)
static void uart_set_baudrate(uart_hw_t *uart, uint32_t src_clk, uint32_t baudrate)
{
uint32_t addr, val;
uart_set_baudrate(uart_id, clock_peri_get_freq(), cfg->baudrate);
addr = UART0_BASE + UART_UARTLCR_H_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= ~UART_UARTLCR_H_BRK;
if (cfg->parity == UART_PARITY_ODD) {
val |= UART_UARTLCR_H_SPS;
val &= ~UART_UARTLCR_H_SPS;
val &= ~UART_UARTLCR_H_EPS;
} else if (cfg->parity == UART_PARITY_EVEN) {
val |= UART_UARTLCR_H_SPS;
val &= ~UART_UARTLCR_H_SPS;
val |= UART_UARTLCR_H_EPS;
} else if (cfg->parity == UART_PARITY_MARK0) {
val |= UART_UARTLCR_H_SPS;
val |= UART_UARTLCR_H_SPS;
val |= UART_UARTLCR_H_EPS;
} else if (cfg->parity == UART_PARITY_MARK1) {
val |= UART_UARTLCR_H_SPS;
val |= UART_UARTLCR_H_SPS;
val &= ~UART_UARTLCR_H_EPS;
} else {
val &= ~UART_UARTLCR_H_PEN;
val &= ~UART_UARTLCR_H_SPS;
val &= ~UART_UARTLCR_H_EPS;
}
if (cfg->stop_bits == UART_STOPBITS_2) {
val |= UART_UARTLCR_H_STP2;
} else {
val &= ~UART_UARTLCR_H_STP2;
}
val &= ~UART_UARTLCR_H_WLEN_MASK;
val |= (cfg->data_bits << UART_UARTLCR_H_WLEN_POS);
putreg32(val, addr);
addr = UART0_BASE + UART_UARTCR_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val |= UART_UARTCR_UARTEN;
val &= ~UART_UARTCR_SIREN;
val &= ~UART_UARTCR_SIRLP;
val &= ~UART_UARTCR_LBE;
val &= ~UART_UARTCR_DTR;
val &= ~UART_UARTCR_RTS;
val &= ~UART_UARTCR_OUT1;
val &= ~UART_UARTCR_OUT2;
val &= ~UART_UARTCR_RTSEN;
val &= ~UART_UARTCR_CTSEN;
if (cfg->mode == UART_MODE_NONE) {
val &= ~UART_UARTCR_TXE;
val &= ~UART_UARTCR_RXE;
} else if (cfg->mode == UART_MODE_TX_ONLY) {
val |= UART_UARTCR_TXE;
val &= ~UART_UARTCR_RXE;
} else if (cfg->mode == UART_MODE_RX_ONLY) {
val &= ~UART_UARTCR_TXE;
val |= UART_UARTCR_RXE;
} else {
val |= UART_UARTCR_TXE;
val |= UART_UARTCR_RXE;
}
putreg32(val, addr);
addr = UART0_BASE + UART_UARTLCR_H_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
if (cfg->fifo_enable) {
val |= UART_UARTLCR_H_FEN;
} else {
val &= ~UART_UARTLCR_H_FEN;
}
putreg32(val, addr);
addr = UART0_BASE + UART_UARTIFLS_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= ~UART_UARTIFLS_TXIFLSEL_MASK;
val |= (cfg->tx_fifo_level << UART_UARTIFLS_TXIFLSEL_POS);
val &= ~UART_UARTIFLS_RXIFLSEL_MASK;
val |= (cfg->rx_fifo_level << UART_UARTIFLS_RXIFLSEL_POS);
putreg32(val, addr);
}
void uart_set_baudrate(uint8_t uart_id, uint32_t src_clk, uint32_t baudrate)
{
uint32_t addr, val;
uint32_t baud_rate_div, baud_ibrd, baud_fbrd;
baud_rate_div = 8 * src_clk / baudrate;
@ -101,119 +17,80 @@ void uart_set_baudrate(uint8_t uart_id, uint32_t src_clk, uint32_t baudrate)
} else {
baud_fbrd = ((baud_rate_div & 0x7F) + 1) / 2;
}
addr = UART0_BASE + UART_UARTIBRD_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= ~UART_UARTIBRD_BAUD_DIVINT_MASK;
val |= (baud_ibrd << UART_UARTIBRD_BAUD_DIVINT_POS);
putreg32(val, addr);
addr = UART0_BASE + UART_UARTFBRD_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= ~UART_UARTFBRD_BAUD_DIVFRAC_MASK;
val |= (baud_fbrd << UART_UARTFBRD_BAUD_DIVFRAC_POS);
putreg32(val, addr);
uart->ibrd = baud_ibrd;
uart->fbrd = baud_fbrd;
}
uint32_t uart_get_flags(uint8_t uart_id)
void uart_init(uart_hw_t *uart, uint32_t baudrate, uint32_t cfg)
{
return getreg32(UART0_BASE + UART_UARTFR_OFFSET + (UART1_BASE - UART0_BASE) * uart_id);
uart_set_baudrate(uart, clock_peri_get_freq(), baudrate);
uart->lcr_h = cfg | UART_UARTLCR_H_FEN;
uart->cr = UART_UARTCR_UARTEN | UART_UARTCR_TXE | UART_UARTCR_RXE;
uart->ifls = (2 << UART_UARTIFLS_TXIFLSEL_POS) | (2 << UART_UARTIFLS_RXIFLSEL_POS);
}
void uart_write_block(uint8_t uart_id, uint8_t *data, uint32_t length)
uint32_t uart_get_flags(uart_hw_t *uart)
{
return uart->fr;
}
void uart_write_block(uart_hw_t *uart, uint8_t *data, uint32_t length)
{
uint32_t addr;
uint32_t flag, idx;
idx = 0;
addr = UART0_BASE + UART_UARTDR_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
while (idx < length) {
flag = uart_get_flags(uart_id);
flag = uart_get_flags(uart);
if (!(flag & UART_FLAG_TXFF)) {
putreg32(data[idx++], addr);
uart->dr = data[idx++];
}
}
}
int uart_put_char(uint8_t uart_id, uint8_t c)
int uart_put_char(uart_hw_t *uart, uint8_t c)
{
uint32_t addr;
if (uart_get_flags(UART_ID_0) & UART_FLAG_TXFF) {
if (uart_get_flags(uart) & UART_FLAG_TXFF) {
return -1;
}
addr = UART0_BASE + UART_UARTDR_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
putreg32(c, addr);
uart->dr = c;
return (int)c;
}
int uart_get_char(uint8_t uart_id)
int uart_get_char(uart_hw_t *uart)
{
uint32_t addr, val;
if (uart_get_flags(UART_ID_0) & UART_FLAG_RXFE) {
if (uart_get_flags(uart) & UART_FLAG_RXFE) {
return -1;
}
addr = UART0_BASE + UART_UARTDR_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= UART_UARTDR_DATA_MASK;
val >>= UART_UARTDR_DATA_POS;
return (int)val;
return (int)(uart->dr & 0xFF);
}
uint32_t uart_int_get_raw_status(uint8_t uart_id)
uint32_t uart_int_get_raw_status(uart_hw_t *uart)
{
uint32_t addr, val;
addr = UART0_BASE + UART_UARTRIS_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= UART_INT_ALL;
return val;
return (uart->ris & UART_INT_ALL);
}
uint32_t uart_int_get_status(uint8_t uart_id)
uint32_t uart_int_get_status(uart_hw_t *uart)
{
uint32_t addr, val;
addr = UART0_BASE + UART_UARTMIS_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= UART_INT_ALL;
return val;
return (uart->mis & UART_INT_ALL);
}
void uart_int_clear(uint8_t uart_id, uint32_t int_type)
void uart_int_clear(uart_hw_t *uart, uint32_t int_type)
{
uint32_t addr, val;
addr = UART0_BASE + UART_UARTICR_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = int_type & UART_INT_ALL;
putreg32(val, addr);
uart->icr = (int_type & UART_INT_ALL);
}
void uart_int_enable(uint8_t uart_id, uint32_t int_type)
void uart_int_enable(uart_hw_t *uart, uint32_t int_type)
{
uint32_t addr, val;
addr = UART0_BASE + UART_UARTIMSC_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val |= (int_type & UART_INT_ALL);
putreg32(val, addr);
hw_set_bits(&uart->imsc, int_type & UART_INT_ALL);
}
void uart_int_disable(uint8_t uart_id, uint32_t int_type)
void uart_int_disable(uart_hw_t *uart, uint32_t int_type)
{
uint32_t addr, val;
addr = UART0_BASE + UART_UARTIMSC_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= ~(int_type & UART_INT_ALL);
putreg32(val, addr);
hw_clear_bits(&uart->imsc, int_type & UART_INT_ALL);
}
uint32_t uart_int_get_mask_status(uint8_t uart_id)
uint32_t uart_int_get_mask_status(uart_hw_t *uart)
{
uint32_t addr, val;
addr = UART0_BASE + UART_UARTIMSC_OFFSET + (UART1_BASE - UART0_BASE) * uart_id;
val = getreg32(addr);
val &= UART_INT_ALL;
return val;
return (uart->imsc & UART_INT_ALL);
}

31
example/boot2/main.c
View File

@ -61,28 +61,19 @@ void __attribute__((section(".text.boot2_pre"))) boot2_copy_self(void)
#include "timer.h"
#include "jump.h"
#define UART_ID uart0_hw
uint8_t tx_buffer[512] __attribute__((aligned(4)));
uint8_t rx_buffer[512] __attribute__((aligned(4)));
struct uart_cfg_s uart_cfg = {
.baudrate = 750 * 1000,
.mode = UART_MODE_TX_RX,
.data_bits = UART_DATABITS_8,
.parity = UART_PARITY_NONE,
.stop_bits = UART_STOPBITS_1,
.fifo_enable = ENABLE,
.tx_fifo_level = UART_FIFO_LEVEL_1_2,
.rx_fifo_level = UART_FIFO_LEVEL_1_2,
};
void process_return_ok(void)
{
uart_write_block(UART_ID_0, (uint8_t *)"OKAY", 4);
uart_write_block(UART_ID, (uint8_t *)"OKAY", 4);
}
void process_return_fail(void)
{
uart_write_block(UART_ID_0, (uint8_t *)"FAIL", 4);
uart_write_block(UART_ID, (uint8_t *)"FAIL", 4);
}
void process_flash_erase(uint32_t addr, uint32_t length)
@ -125,13 +116,13 @@ void process_flash_read(uint32_t addr, uint8_t *data, uint32_t length)
{
while (length >= FLASH_READ_SIZE) {
flash_read(addr, data, FLASH_READ_SIZE);
uart_write_block(UART_ID_0, data, FLASH_READ_SIZE);
uart_write_block(UART_ID, data, FLASH_READ_SIZE);
addr += FLASH_READ_SIZE;
length -= FLASH_READ_SIZE;
}
if (length > 0) {
flash_read(addr, data, length);
uart_write_block(UART_ID_0, data, length);
uart_write_block(UART_ID, data, length);
}
}
@ -173,13 +164,13 @@ void uart_process(uint16_t code, uint16_t length)
}
}
void uart_state_machine(uint8_t id)
void uart_state_machine(uart_hw_t *uart)
{
static uint64_t time_fifo_empty = 0;
static uint16_t uart_rx_length = 0;
uint16_t code, code_inv, length, length_inv;
if (uart_get_flags(id) & UART_FLAG_RXFE) {
if (uart_get_flags(uart) & UART_FLAG_RXFE) {
if (timer_count_read() - time_fifo_empty < 100) {
return;
}
@ -220,7 +211,7 @@ int main(void)
reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER);
gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA); /* UART_TX pin */
gpio_init(1, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_SCHMITT | GPIO_PAD_IE | GPIO_PAD_OD); /* UART_RX pin */
uart_init(UART_ID_0, &uart_cfg);
uart_init(uart0_hw, 750 * 1000, UART_DATABITS_8 | UART_PARITY_NONE | UART_STOPBITS_1);
watchdog_start_tick(12); /* 12MHz / 12 = 1MHz, as 1us */
timer_start();
@ -238,9 +229,9 @@ int main(void)
for (uint32_t i = 0; i < 4; i++) {
tx_buffer[i] = 0x55;
}
uart_write_block(UART_ID_0, tx_buffer, 4);
uart_write_block(UART_ID, tx_buffer, 4);
while (1) {
uart_state_machine(UART_ID_0);
uart_state_machine(UART_ID);
}
} else {
flash_read(FW_ADDRESS, rx_buffer, FLASH_READ_SIZE);

15
example/peripherals/dma/dma_sniff/main.c
View File

@ -32,24 +32,13 @@ struct dma_sniff_cfg_s sniff_cfg = {
.out_inv = ENABLE,
};
struct uart_cfg_s uart_cfg = {
.baudrate = 2 * 1000 * 1000,
.mode = UART_MODE_TX_RX,
.data_bits = UART_DATABITS_8,
.parity = UART_PARITY_NONE,
.stop_bits = UART_STOPBITS_1,
.fifo_enable = ENABLE,
.tx_fifo_level = UART_FIFO_LEVEL_1_2,
.rx_fifo_level = UART_FIFO_LEVEL_1_2,
};
int main(void)
{
uint32_t sniff_result;
reset_unreset_blocks_wait(RESETS_BLOCK_DMA);
reset_unreset_blocks_wait(RESETS_BLOCK_UART0 | RESETS_BLOCK_DMA);
gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA);
uart_init(UART_ID_0, &uart_cfg);
uart_init(uart0_hw, 2 * 1000 * 1000, UART_DATABITS_8 | UART_PARITY_NONE | UART_STOPBITS_1);
for (int i = 0; i < sizeof(dma_buffer_calc); i++) {
dma_buffer_calc[i] = 0;

9
example/peripherals/uart/uart_loopback/CMakeLists.txt Normal file
View File

@ -0,0 +1,9 @@
cmake_minimum_required(VERSION 3.10)
include(proj.conf)
project(${EXAMPLE_NAME} VERSION 0.1)
add_executable(${EXAMPLE_NAME}.elf main.c)
add_subdirectory(${SDK_BASE_DIR} sdk)
target_link_libraries(${EXAMPLE_NAME}.elf sdk)

18
example/peripherals/uart/uart_loopback/Makefile Normal file
View File

@ -0,0 +1,18 @@
EXAMPLE_BASE_DIR ?= $(shell realpath .)
EXAMPLE_NAME := $(notdir $(patsubst %/,%,$(CURDIR)))
SDK_BASE_DIR ?= $(shell realpath ./../../../..)
export SDK_BASE_DIR
export EXAMPLE_NAME
export EXAMPLE_BASE_DIR
GCC_PATH := $(shell which arm-none-eabi-gcc)
CROSS_COMPILE := $(patsubst %gcc,%,$(GCC_PATH))
ifeq ($(GCC_PATH),)
$(error arm-none-eabi-gcc not found in PATH. Please install the ARM toolchain.)
endif
# add custom cmake definition
#cmake_definition+=-Dxxx=sss
include $(SDK_BASE_DIR)/project.build

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example/peripherals/uart/uart_loopback/main.c Normal file
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#include "gpio.h"
#include "uart.h"
#include "resets.h"
#include "stdio.h"
#define UART_ID uart0_hw
int main(void)
{
reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_UART0);
gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA); /* UART_TX pin */
gpio_init(1, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_SCHMITT | GPIO_PAD_IE | GPIO_PAD_OD); /* UART_RX pin */
uart_init(UART_ID, 2 * 1000 * 1000, UART_DATABITS_8 | UART_PARITY_NONE | UART_STOPBITS_1);
printf("uart_loopback example\r\n");
while (1) {
int c = uart_get_char(UART_ID);
if (c < 0) {
continue;
}
uart_put_char(UART_ID, (uint8_t)c);
}
return 0;
}

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example/peripherals/uart/uart_loopback/proj.conf Normal file
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# set(CONFIG_COMPONENT1 1)