[update] move init to system_init()

This commit is contained in:
zhji 2025-03-29 16:53:16 +08:00
parent e408c7bca5
commit ad3d3db97b
4 changed files with 42 additions and 24 deletions

View File

@ -49,6 +49,8 @@ void system_wdg_bound(uint32_t block);
void system_wdg_unbound(uint32_t block); void system_wdg_unbound(uint32_t block);
uint8_t system_block_is_available(uint32_t block); uint8_t system_block_is_available(uint32_t block);
void system_init(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

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@ -1,4 +1,11 @@
#include "system.h" #include "system.h"
#include "clock.h"
#include "resets.h"
#include "irq.h"
#include "gpio.h"
#include "timer.h"
#include "uart.h"
#include "stdio.h"
/* voltage: SYSTEM_REGULATOR_VOLTAGE_XXX */ /* voltage: SYSTEM_REGULATOR_VOLTAGE_XXX */
void system_regulator_set(uint8_t voltage) void system_regulator_set(uint8_t voltage)
@ -84,3 +91,32 @@ uint8_t system_block_is_available(uint32_t block)
return 0; return 0;
} }
} }
void system_init(void)
{
struct uart_cfg_s uart_cfg = {
.baudrate = 6 * 1000 * 1000,
.mode = UART_MODE_TX_RX,
.data_bits = UART_DATABITS_8,
.parity = UART_PARITY_NONE,
.stop_bits = UART_STOPBITS_1,
.fifo_enable = ENABLE,
.tx_fifo_level = UART_FIFO_LEVEL_1_2,
.rx_fifo_level = UART_FIFO_LEVEL_1_2,
};
system_regulator_set(SYSTEM_REGULATOR_VOLTAGE_1P30V);
clock_ref_set_src(CLOCK_REF_SRC_XOSC_GLITCHLESS);
clock_sys_set_src(CLOCK_SYS_SRC_REF_GLITCHLESS);
/* refdiv >= 5MHz, VCO=[750:1600]MHz, fbdiv=[16:320], postdiv=[1:7] */
clock_pll_init(CLOCK_PLL_SYSPLL, 1, 100, 3, 2); /* 12MHz / 1 * 100 / 3 / 2 = 200MHz */
clock_sys_set_div(1 << 8); /* 200MHz / 1 = 200MHz */
clock_sys_set_src(CLOCK_SYS_SRC_SYSPLL);
clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL);
reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER);
uart_init(UART_ID_0, &uart_cfg);
gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE);
timer_start();
irq_init();
printf("system clock = 200MHz\r\n");
}

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@ -52,7 +52,7 @@ isr_reset:
cmp r1, r2 cmp r1, r2
blo 1b blo 1b
2: 2:
bl SystemInit ; bl SystemInit
bl main bl main
b . b .
.size isr_reset, .-isr_reset .size isr_reset, .-isr_reset

View File

@ -1,26 +1,12 @@
#include "resets.h" #include "system.h"
#include "clock.h"
#include "irq.h" #include "irq.h"
#include "gpio.h"
#include "uart.h"
#include "timer.h" #include "timer.h"
#include "stdio.h" #include "stdio.h"
#include "RP2040.h"
#define TIMER_ALARM_ID TIMER_ALARM_0 #define TIMER_ALARM_ID TIMER_ALARM_0
#define TIMER_PERIOD_US (1000 * 1000) #define TIMER_PERIOD_US (1000 * 1000)
struct uart_cfg_s uart_cfg = {
.baudrate = 6 * 1000 * 1000,
.mode = UART_MODE_TX_RX,
.data_bits = UART_DATABITS_8,
.parity = UART_PARITY_NONE,
.stop_bits = UART_STOPBITS_1,
.fifo_enable = ENABLE,
.tx_fifo_level = UART_FIFO_LEVEL_1_2,
.rx_fifo_level = UART_FIFO_LEVEL_1_2,
};
void timer_alarm_0_isr(void) void timer_alarm_0_isr(void)
{ {
timer_int_clear(TIMER_ALARM_ID); timer_int_clear(TIMER_ALARM_ID);
@ -30,13 +16,7 @@ void timer_alarm_0_isr(void)
int main(void) int main(void)
{ {
reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER); system_init();
gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE);
__enable_irq();
uart_init(UART_ID_0, &uart_cfg);
printf("timer interrupt example.\r\n");
irq_init();
timer_count_write(0); timer_count_write(0);
timer_alarm_set(TIMER_ALARM_ID, TIMER_PERIOD_US); timer_alarm_set(TIMER_ALARM_ID, TIMER_PERIOD_US);
timer_int_enable(TIMER_ALARM_ID); timer_int_enable(TIMER_ALARM_ID);