From ea852b4dd76bb7b1a74d25a84bf16021b39018fa Mon Sep 17 00:00:00 2001 From: zhji Date: Sat, 31 May 2025 21:33:48 +0800 Subject: [PATCH] [feat] update gpio --- driver/inc/gpio.h | 129 +++++-------- driver/inc/reg/gpio_reg.h | 83 +-------- driver/src/gpio.c | 219 ++--------------------- driver/src/system.c | 2 +- example/boot2/main.c | 14 +- example/boot2/src/flash.c | 22 +-- example/peripherals/dma/dma_sniff/main.c | 2 +- 7 files changed, 76 insertions(+), 395 deletions(-) diff --git a/driver/inc/gpio.h b/driver/inc/gpio.h index ba29946..5ef71c2 100644 --- a/driver/inc/gpio.h +++ b/driver/inc/gpio.h @@ -3,110 +3,67 @@ #include "reg.h" #include "gpio_reg.h" -#include "sio_reg.h" -#define GPIO_SIO_DIR_IN (0) -#define GPIO_SIO_DIR_OUT (1) +#define GPIO_FUNC_XIP (0 << 0U) /* not available for GPIO0~29 */ +#define GPIO_FUNC_SPI (1 << 0U) /* only available for GPIO0~29 */ +#define GPIO_FUNC_UART (2 << 0U) /* only available for GPIO0~29 */ +#define GPIO_FUNC_I2C (3 << 0U) /* only available for GPIO0~29 */ +#define GPIO_FUNC_PWM (4 << 0U) /* only available for GPIO0~29 */ +#define GPIO_FUNC_SIO (5 << 0U) /* available for all GPIO */ +#define GPIO_FUNC_PIO0 (6 << 0U) /* only available for GPIO0~29 */ +#define GPIO_FUNC_PIO1 (7 << 0U) /* only available for GPIO0~29 */ +#define GPIO_FUNC_CLOCK (8 << 0U) /* only available for GPIO20~25 */ +#define GPIO_FUNC_USB (9 << 0U) +#define GPIO_FUNC_NULL (0x1F << 0U) -#define GPIO_FUNC_XIP (0) /* not available for GPIO0~29 */ -#define GPIO_FUNC_SPI (1) /* only available for GPIO0~29 */ -#define GPIO_FUNC_UART (2) /* only available for GPIO0~29 */ -#define GPIO_FUNC_I2C (3) /* only available for GPIO0~29 */ -#define GPIO_FUNC_PWM (4) /* only available for GPIO0~29 */ -#define GPIO_FUNC_SIO (5) /* available for all GPIO */ -#define GPIO_FUNC_PIO0 (6) /* only available for GPIO0~29 */ -#define GPIO_FUNC_PIO1 (7) /* only available for GPIO0~29 */ -#define GPIO_FUNC_CLOCK (8) /* only available for GPIO20~25 */ -#define GPIO_FUNC_USB (9) -#define GPIO_FUNC_NULL (31) +#define GPIO_OVER_OUT_NORMAL (0 << 8U) +#define GPIO_OVER_OUT_INVERSE (1 << 8U) +#define GPIO_OVER_OUT_LOW (2 << 8U) +#define GPIO_OVER_OUT_HIGH (3 << 8U) -#define GPIO_IRQ_NULL (0) -#define GPIO_IRQ_LEVEL_LOW (1) -#define GPIO_IRQ_LEVEL_HIGH (2) -#define GPIO_IRQ_EDGE_FALL (4) -#define GPIO_IRQ_EDGE_RISE (8) +#define GPIO_OVER_OE_NORMAL (0 << 12U) +#define GPIO_OVER_OE_INVERSE (1 << 12U) +#define GPIO_OVER_OE_DISABLE (2 << 12U) +#define GPIO_OVER_OE_ENABLE (3 << 12U) -#define GPIO_OVER_OUT_PERIPHERAL (0) -#define GPIO_OVER_OUT_PERIPHERAL_INVERSE (1) -#define GPIO_OVER_OUT_FORCE_LOW (2) -#define GPIO_OVER_OUT_FORCE_HIGH (3) +#define GPIO_OVER_IN_NORMAL (0 << 16U) +#define GPIO_OVER_IN_INVERSE (1 << 16U) +#define GPIO_OVER_IN_LOW (2 << 16U) +#define GPIO_OVER_IN_HIGH (3 << 16U) -#define GPIO_OVER_OE_PERIPHERAL (0) -#define GPIO_OVER_OE_PERIPHERAL_INVERSE (1) -#define GPIO_OVER_OE_FORCE_DISABLE (2) -#define GPIO_OVER_OE_FORCE_ENABLE (3) +#define GPIO_OVER_IRQ_NORMAL (0 << 2U) +#define GPIO_OVER_IRQ_INVERSE (1 << 2U) +#define GPIO_OVER_IRQ_LOW (2 << 2U) +#define GPIO_OVER_IRQ_HIGH (3 << 2U) -#define GPIO_OVER_IN_PERIPHERAL (0) -#define GPIO_OVER_IN_PERIPHERAL_INVERSE (1) -#define GPIO_OVER_IN_FORCE_LOW (2) -#define GPIO_OVER_IN_FORCE_HIGH (3) +#define GPIO_SLEW_FAST (1ULL << (0 + 32)) +#define GPIO_SCHMITT (1ULL << (1 + 32)) +#define GPIO_PULL_DOWN (1ULL << (2 + 32)) +#define GPIO_PULL_UP (1ULL << (3 + 32)) +#define GPIO_DRIVE_2MA (0ULL << (4 + 32)) +#define GPIO_DRIVE_4MA (1ULL << (4 + 32)) +#define GPIO_DRIVE_8MA (2ULL << (4 + 32)) +#define GPIO_DRIVE_12MA (3ULL << (4 + 32)) +#define GPIO_PAD_IE (1ULL << (6 + 32)) +#define GPIO_PAD_OD (1ULL << (7 + 32)) -#define GPIO_OVER_IRQ_NORMAL (0) -#define GPIO_OVER_IRQ_INVERSE (1) -#define GPIO_OVER_IRQ_FORCE_LOW (2) -#define GPIO_OVER_IRQ_FORCE_HIGH (3) +#define GPIO_IRQ_NULL (0) +#define GPIO_IRQ_LEVEL_LOW (1) +#define GPIO_IRQ_LEVEL_HIGH (2) +#define GPIO_IRQ_EDGE_FALL (4) +#define GPIO_IRQ_EDGE_RISE (8) #define GPIO_PADS_VOLTAGE_3V3 (0) #define GPIO_PADS_VOLTAGE_1V8 (1) -#define GPIO_PADS_DRIVE_STRENGTH_2MA (0) -#define GPIO_PADS_DRIVE_STRENGTH_4MA (1) -#define GPIO_PADS_DRIVE_STRENGTH_8MA (2) -#define GPIO_PADS_DRIVE_STRENGTH_12MA (3) - -#define GPIO_PADS_SLEW_RATE_SLOW (0) -#define GPIO_PADS_SLEW_RATE_FAST (1) - -struct gpio_cfg_s { - uint8_t pin; - uint8_t sio_dir; /* GPIO_SIO_DIR_XXX */ - uint8_t funcsel; /* GPIO_FUNC_XXX */ - uint8_t over_out; /* GPIO_OVER_OUT_XXX */ - uint8_t over_oe; /* GPIO_OVER_OE_XXX */ - uint8_t over_in; /* GPIO_OVER_IN_XXX */ - uint8_t over_irq; /* GPIO_OVER_IRQ_XXX */ - uint8_t slew_rate; /* slew rate control, slow or fast */ - uint8_t schmitt; /* enable or disable schmitt */ - uint8_t pull_down; /* enable or disable pull down */ - uint8_t pull_up; /* enable or disable pull up */ - uint8_t drive; /* drive strength */ - uint8_t ie; /* enable or disable input */ - uint8_t od; /* output disable, has priority over output enable from peripherals */ -}; - #ifdef __cplusplus extern "C" { #endif uint8_t gpio_read(uint8_t pin); -void gpio_write(uint8_t pin, uint8_t value); void gpio_set(uint8_t pin); void gpio_clear(uint8_t pin); -void gpio_toggle(uint8_t pin); -void gpio_oe_write(uint8_t pin, uint8_t value); -void gpio_oe_set(uint8_t pin); -void gpio_oe_clear(uint8_t pin); -void gpio_oe_toggle(uint8_t pin); - -uint32_t gpio_read_multi(void); -void gpio_write_multi(uint32_t value); -void gpio_set_multi(uint32_t pins); -void gpio_clear_multi(uint32_t pins); -void gpio_toggle_multi(uint32_t pins); -void gpio_oe_write_multi(uint32_t value); -void gpio_oe_set_multi(uint32_t pins); -void gpio_oe_clear_multi(uint32_t pins); -void gpio_oe_toggle_multi(uint32_t pins); - -uint32_t gpio_get_status(uint8_t pin, uint32_t status); -void gpio_func_sel(uint8_t pin, uint8_t func); -void gpio_over_out_set(uint8_t pin, uint8_t over); -void gpio_over_oe_set(uint8_t pin, uint8_t over); -void gpio_over_in_set(uint8_t pin, uint8_t over); -void gpio_over_irq_set(uint8_t pin, uint8_t over); - -void gpio_init(struct gpio_cfg_s *cfg); -void gpio_init_simple(uint8_t pin, uint8_t func, uint8_t pulldown, uint8_t pullup); +void gpio_init(uint8_t pin, uint64_t cfg); uint8_t gpio_irq_get_raw_status(uint8_t pin, uint8_t irq); void gpio_irq_raw_status_clear(uint8_t pin, uint8_t irq); diff --git a/driver/inc/reg/gpio_reg.h b/driver/inc/reg/gpio_reg.h index 381c25f..2d692a6 100644 --- a/driver/inc/reg/gpio_reg.h +++ b/driver/inc/reg/gpio_reg.h @@ -15,45 +15,6 @@ #define GPIO_INTF_DORMANT_WAKE_OFFSET (0x170) /* interrupt force for dormant_wake */ #define GPIO_INTS_DORMANT_WAKE_OFFSET (0x180) /* interrupt status after masking & forcing for dormant_wake */ -/* IO_QSPI_BASE @0x40018000 */ -#define GPIO_QSPI_CLK_STATUS_OFFSET (0x000) /* QSPI CLK GPIO status */ -#define GPIO_QSPI_CLK_CTRL_OFFSET (0x004) /* QSPI CLK GPIO control including function select and overrides */ -#define GPIO_QSPI_CS_STATUS_OFFSET (0x008) /* QSPI CS GPIO status */ -#define GPIO_QSPI_CS_CTRL_OFFSET (0x00C) /* QSPI CS GPIO control including function select and overrides */ -#define GPIO_QSPI_IO0_STATUS_OFFSET (0x010) /* QSPI IO0 GPIO status */ -#define GPIO_QSPI_IO0_CTRL_OFFSET (0x014) /* QSPI IO0 GPIO control including function select and overrides */ -#define GPIO_QSPI_IO1_STATUS_OFFSET (0x018) /* QSPI IO1 GPIO status */ -#define GPIO_QSPI_IO1_CTRL_OFFSET (0x01C) /* QSPI IO1 GPIO control including function select and overrides */ -#define GPIO_QSPI_IO2_STATUS_OFFSET (0x020) /* QSPI IO2 GPIO status */ -#define GPIO_QSPI_IO2_CTRL_OFFSET (0x024) /* QSPI IO2 GPIO control including function select and overrides */ -#define GPIO_QSPI_IO3_STATUS_OFFSET (0x028) /* QSPI IO3 GPIO status */ -#define GPIO_QSPI_IO3_CTRL_OFFSET (0x02C) /* QSPI IO3 GPIO control including function select and overrides */ -#define GPIO_QSPI_INTR_OFFSET (0x030) /* raw interrupts */ -#define GPIO_QSPI_INTE_PROC0_OFFSET (0x034) /* interrupt enable for proc0 */ -#define GPIO_QSPI_INTF_PROC0_OFFSET (0x038) /* interrupt force for proc0 */ -#define GPIO_QSPI_INTS_PROC0_OFFSET (0x03C) /* interrupt status after masking & forcing for proc0 */ -#define GPIO_QSPI_INTE_PROC1_OFFSET (0x040) /* interrupt enable for proc1 */ -#define GPIO_QSPI_INTF_PROC1_OFFSET (0x044) /* interrupt force for proc1 */ -#define GPIO_QSPI_INTS_PROC1_OFFSET (0x048) /* interrupt status after masking & forcing for proc1 */ -#define GPIO_QSPI_INTE_DORMANT_WAKE_OFFSET (0x04C) /* interrupt enable for dormant_wake */ -#define GPIO_QSPI_INTF_DORMANT_WAKE_OFFSET (0x050) /* interrupt force for dormant_wake */ -#define GPIO_QSPI_INTS_DORMANT_WAKE_OFFSET (0x054) /* interrupt status after masking & forcing for dormant_wake */ - -/* PADS_BANK0_BASE @0x4001C000 */ -#define GPIO_PADS_VOLTAGE_SELECT_OFFSET (0x000) -#define GPIO_PADS_CTRL_OFFSET (0x004) /* pad control register */ -#define GPIO_PADS_SWCLK_CTRL_OFFSET (0x07C) -#define GPIO_PADS_SWDIO_CTRL_OFFSET (0x080) - -/* PADS_QSPI_BASE @0x40020000 */ -#define GPIO_PADS_QSPI_VOLTAGE_SELECT_OFFSET (0x000) -#define GPIO_PADS_QSPI_CLK_CTRL_OFFSET (0x004) -#define GPIO_PADS_QSPI_IO0_CTRL_OFFSET (0x008) -#define GPIO_PADS_QSPI_IO1_CTRL_OFFSET (0x00C) -#define GPIO_PADS_QSPI_IO2_CTRL_OFFSET (0x010) -#define GPIO_PADS_QSPI_IO3_CTRL_OFFSET (0x014) -#define GPIO_PADS_QSPI_CS_CTRL_OFFSET (0x018) - /* GPIO_STATUS_OFFSET */ #define GPIO_STATUS_OE_FROM_PERI (1 << 12) #define GPIO_STATUS_OE_TO_PAD (1 << 13) @@ -61,43 +22,13 @@ #define GPIO_STATUS_IN_TO_PERI (1 << 19) #define GPIO_STATUS_IRQ_FROM_PAD (1 << 24) #define GPIO_STATUS_IRQ_TO_PROC (1 << 26) -#define GPIO_STATUS_ALL (GPIO_STATUS_OE_FROM_PERI | \ - GPIO_STATUS_OE_TO_PAD | \ - GPIO_STATUS_IN_FROM_PAD | \ - GPIO_STATUS_IN_TO_PERI | \ - GPIO_STATUS_IRQ_FROM_PAD | \ - GPIO_STATUS_IRQ_TO_PROC) - -/* GPIO_CTRL_OFFSET */ -#define GPIO_FUNC_POS (0) -#define GPIO_FUNC_MASK (0x1F) -#define GPIO_OVER_OUT_POS (8) -#define GPIO_OVER_OUT_MASK (3) -#define GPIO_OVER_OE_POS (12) -#define GPIO_OVER_OE_MASK (3) -#define GPIO_OVER_IN_POS (16) -#define GPIO_OVER_IN_MASK (3) -#define GPIO_OVER_IRQ_POS (28) -#define GPIO_OVER_IRQ_MASK (3) - -/* GPIO_PADS_CTRL_OFFSET */ -#define GPIO_PADS_SLEW_RATE_POS (0) -#define GPIO_PADS_SCHMITT_POS (1) -#define GPIO_PADS_PULL_DOWN_POS (2) -#define GPIO_PADS_PULL_UP_POS (3) -#define GPIO_PADS_DRIVE_POS (4) -#define GPIO_PADS_DRIVE_MASK (3) -#define GPIO_PADS_IE_POS (6) -#define GPIO_PADS_OD_POS (7) typedef struct { io_rw_32 voltage_select; io_rw_32 io[30]; } pads_bank0_hw_t; -#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) -#define pads_bank0_hw_set ((pads_bank0_hw_t *const)hw_set_alias_untyped(pads_bank0_hw)) -#define pads_bank0_hw_clear ((pads_bank0_hw_t *const)hw_clear_alias_untyped(pads_bank0_hw)) +#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) typedef struct { io_rw_32 voltage_select; @@ -109,9 +40,7 @@ typedef struct { io_rw_32 io_qspi_ss; } pads_qspi_hw_t; -#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) -#define pads_qspi_hw_set ((pads_qspi_hw_t *const)hw_set_alias_untyped(pads_qspi_hw)) -#define pads_qspi_hw_clear ((pads_qspi_hw_t *const)hw_clear_alias_untyped(pads_qspi_hw)) +#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) typedef struct { io_rw_32 inte[4]; @@ -130,9 +59,7 @@ typedef struct { io_irq_ctrl_hw_t dormant_wake_irq_ctrl; } iobank0_hw_t; -#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) -#define iobank0_hw_set ((iobank0_hw_t *const)hw_set_alias_untyped(iobank0_hw)) -#define iobank0_hw_clear ((iobank0_hw_t *const)hw_clear_alias_untyped(iobank0_hw)) +#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) typedef struct { struct { @@ -141,9 +68,7 @@ typedef struct { } io[6]; } ioqspi_hw_t; -#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) -#define ioqspi_hw_set ((ioqspi_hw_t *const)hw_set_alias_untyped(ioqspi_hw)) -#define ioqspi_hw_clear ((ioqspi_hw_t *const)hw_clear_alias_untyped(ioqspi_hw)) +#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) #ifdef __cplusplus extern "C" { diff --git a/driver/src/gpio.c b/driver/src/gpio.c index 8b74d95..697e1ff 100644 --- a/driver/src/gpio.c +++ b/driver/src/gpio.c @@ -4,228 +4,37 @@ uint8_t gpio_read(uint8_t pin) { uint32_t val; - val = getreg32(SIO_BASE + SIO_GPIO_IN_OFFSET); - val = val & (1 << pin); - if (val) { + val = iobank0_hw->io[pin].status; + if (val & GPIO_STATUS_IN_FROM_PAD) { return 1; } else { return 0; } } -void gpio_write(uint8_t pin, uint8_t value) -{ - if (value) { - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OUT_SET_OFFSET); - } else { - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OUT_CLR_OFFSET); - } -} - void gpio_set(uint8_t pin) { - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OUT_SET_OFFSET); + hw_set_bits(&(iobank0_hw->io[pin].ctrl), GPIO_OVER_OUT_HIGH); } void gpio_clear(uint8_t pin) { - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OUT_CLR_OFFSET); + uint32_t val; + + val = iobank0_hw->io[pin].ctrl; + val &= ~GPIO_OVER_OUT_HIGH; + val |= GPIO_OVER_OUT_LOW; + iobank0_hw->io[pin].ctrl = val; } -void gpio_toggle(uint8_t pin) -{ - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OUT_XOR_OFFSET); -} - -void gpio_oe_write(uint8_t pin, uint8_t value) -{ - if (value) { - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OE_SET_OFFSET); - } else { - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OE_CLR_OFFSET); - } -} - -void gpio_oe_set(uint8_t pin) -{ - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OE_SET_OFFSET); -} - -void gpio_oe_clear(uint8_t pin) -{ - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OE_CLR_OFFSET); -} - -void gpio_oe_toggle(uint8_t pin) -{ - putreg32(1 << pin, SIO_BASE + SIO_GPIO_OE_XOR_OFFSET); -} - -uint32_t gpio_read_multi(void) -{ - return getreg32(SIO_BASE + SIO_GPIO_IN_OFFSET); -} - -void gpio_write_multi(uint32_t value) -{ - putreg32(value, SIO_BASE + SIO_GPIO_OUT_OFFSET); -} - -void gpio_set_multi(uint32_t pins) -{ - putreg32(pins, SIO_BASE + SIO_GPIO_OUT_SET_OFFSET); -} - -void gpio_clear_multi(uint32_t pins) -{ - putreg32(pins, SIO_BASE + SIO_GPIO_OUT_CLR_OFFSET); -} - -void gpio_toggle_multi(uint32_t pins) -{ - putreg32(pins, SIO_BASE + SIO_GPIO_OUT_XOR_OFFSET); -} - -void gpio_oe_write_multi(uint32_t value) -{ - putreg32(value, SIO_BASE + SIO_GPIO_OE_OFFSET); -} - -void gpio_oe_set_multi(uint32_t pins) -{ - putreg32(pins, SIO_BASE + SIO_GPIO_OE_SET_OFFSET); -} - -void gpio_oe_clear_multi(uint32_t pins) -{ - putreg32(pins, SIO_BASE + SIO_GPIO_OE_CLR_OFFSET); -} - -void gpio_oe_toggle_multi(uint32_t pins) -{ - putreg32(pins, SIO_BASE + SIO_GPIO_OE_XOR_OFFSET); -} - -uint32_t gpio_get_status(uint8_t pin, uint32_t status) +void gpio_init(uint8_t pin, uint64_t cfg) { uint32_t val; - val = getreg32(IO_BANK0_BASE + GPIO_STATUS_OFFSET + pin * 8); - return (val & status); -} - -void gpio_func_sel(uint8_t pin, uint8_t func) -{ - uint32_t addr; - uint32_t val; - - addr = IO_BANK0_BASE + GPIO_CTRL_OFFSET + pin * 8; - val = getreg32(addr); - val &= ~(GPIO_FUNC_MASK << GPIO_FUNC_POS); - val |= (uint32_t)func << GPIO_FUNC_POS; - putreg32(val, addr); -} - -void gpio_over_out_set(uint8_t pin, uint8_t over) -{ - uint32_t addr; - uint32_t val; - - addr = IO_BANK0_BASE + GPIO_CTRL_OFFSET + pin * 8; - val = getreg32(addr); - val &= ~(GPIO_OVER_OUT_MASK << GPIO_OVER_OUT_POS); - val |= (uint32_t)over << GPIO_OVER_OUT_POS; - putreg32(val, addr); -} - -void gpio_over_oe_set(uint8_t pin, uint8_t over) -{ - uint32_t addr; - uint32_t val; - - addr = IO_BANK0_BASE + GPIO_CTRL_OFFSET + pin * 8; - val = getreg32(addr); - val &= ~(GPIO_OVER_OE_MASK << GPIO_OVER_OE_POS); - val |= (uint32_t)over << GPIO_OVER_OE_POS; - putreg32(val, addr); -} - -void gpio_over_in_set(uint8_t pin, uint8_t over) -{ - uint32_t addr; - uint32_t val; - - addr = IO_BANK0_BASE + GPIO_CTRL_OFFSET + pin * 8; - val = getreg32(addr); - val &= ~(GPIO_OVER_IN_MASK << GPIO_OVER_IN_POS); - val |= (uint32_t)over << GPIO_OVER_IN_POS; - putreg32(val, addr); -} - -void gpio_over_irq_set(uint8_t pin, uint8_t over) -{ - uint32_t addr; - uint32_t val; - - addr = IO_BANK0_BASE + GPIO_CTRL_OFFSET + pin * 8; - val = getreg32(addr); - val &= ~(GPIO_OVER_IRQ_MASK << GPIO_OVER_IRQ_POS); - val |= (uint32_t)over << GPIO_OVER_IRQ_POS; - putreg32(val, addr); -} - -void gpio_init(struct gpio_cfg_s *cfg) -{ - uint32_t addr; - uint32_t val; - uint32_t offset; - - if (cfg->sio_dir == GPIO_SIO_DIR_OUT) { - gpio_oe_set(cfg->pin); - } else { - gpio_oe_clear(cfg->pin); - } - - offset = cfg->pin << 3; /* cfg->pin * 8 */ - addr = IO_BANK0_BASE + GPIO_CTRL_OFFSET; - val = cfg->funcsel << GPIO_FUNC_POS; - val |= cfg->over_out << GPIO_OVER_OUT_POS; - val |= cfg->over_oe << GPIO_OVER_OE_POS; - val |= cfg->over_in << GPIO_OVER_IN_POS; - val |= cfg->over_irq << GPIO_OVER_IRQ_POS; - putreg32(val, addr + offset); - - offset = cfg->pin << 2; /* cfg->pin * 4 */ - addr = PADS_BANK0_BASE + GPIO_PADS_CTRL_OFFSET; - val = cfg->slew_rate << GPIO_PADS_SLEW_RATE_POS; - val |= cfg->schmitt << GPIO_PADS_SCHMITT_POS; - val |= cfg->pull_down << GPIO_PADS_PULL_DOWN_POS; - val |= cfg->pull_up << GPIO_PADS_PULL_UP_POS; - val |= cfg->drive << GPIO_PADS_DRIVE_POS; - val |= cfg->ie << GPIO_PADS_IE_POS; - val |= cfg->od << GPIO_PADS_OD_POS; - putreg32(val, addr + offset); -} - -void gpio_init_simple(uint8_t pin, uint8_t func, uint8_t pulldown, uint8_t pullup) -{ - struct gpio_cfg_s cfg = { - .pin = pin, - .sio_dir = GPIO_SIO_DIR_IN, - .funcsel = func, - .over_out = GPIO_OVER_OUT_PERIPHERAL, - .over_oe = GPIO_OVER_OE_PERIPHERAL, - .over_in = GPIO_OVER_IN_PERIPHERAL, - .over_irq = GPIO_OVER_IRQ_NORMAL, - .slew_rate = GPIO_PADS_SLEW_RATE_SLOW, /* slew rate control, slow or fast */ - .schmitt = ENABLE, /* enable or disable schmitt */ - .pull_down = pulldown, /* enable or disable pull down */ - .pull_up = pullup, /* enable or disable pull up */ - .drive = GPIO_PADS_DRIVE_STRENGTH_4MA, /* drive strength */ - .ie = ENABLE, /* enable or disable input */ - .od = DISABLE, /* output disable, has priority over output enable from peripherals */ - }; - gpio_init(&cfg); + val = (uint32_t)((cfg >> 32) & 0xFFFFFFFF); + pads_bank0_hw->io[pin] = val; + val = (uint32_t)(cfg & 0xFFFFFFFF); + iobank0_hw->io[pin].ctrl = val; } uint8_t gpio_irq_get_raw_status(uint8_t pin, uint8_t irq) diff --git a/driver/src/system.c b/driver/src/system.c index 0a305fa..e67b7b4 100644 --- a/driver/src/system.c +++ b/driver/src/system.c @@ -115,7 +115,7 @@ void system_init(void) clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL); reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER); uart_init(UART_ID_0, &uart_cfg); - gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE); + gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA); timer_start(); irq_init(); SysTick->CTRL = 0; diff --git a/example/boot2/main.c b/example/boot2/main.c index 7014d33..f7603b7 100644 --- a/example/boot2/main.c +++ b/example/boot2/main.c @@ -9,15 +9,13 @@ void __attribute__((section(".text.boot2_pre"))) boot2_copy_self(void) extern uint32_t _boot2_copy_self_start_addr; extern uint32_t _boot2_copy_self_end_addr; - io_rw_32 *reg; uint32_t cmd; uint32_t length, tx_count, rx_count, rx_skip; uint8_t *copy_to_addr; uint8_t rxbyte; /* force QSPI_CS low level as selected */ - reg = (io_rw_32 *)(IO_QSPI_BASE + GPIO_QSPI_CS_CTRL_OFFSET); - *reg = GPIO_OVER_OUT_FORCE_LOW << GPIO_OVER_OUT_POS; + ioqspi_hw->io[1].ctrl = GPIO_OVER_OUT_LOW; /* send command and length */ cmd = (BOOT2_FLASHCMD_READ_DATA << 24) | BOOT2_FLASH_OFFSET; @@ -51,7 +49,7 @@ void __attribute__((section(".text.boot2_pre"))) boot2_copy_self(void) } /* force QSPI_CS high level as disselected */ - *reg = GPIO_OVER_OUT_FORCE_HIGH << GPIO_OVER_OUT_POS; + ioqspi_hw->io[1].ctrl = GPIO_OVER_OUT_HIGH; } #include "resets.h" @@ -223,16 +221,16 @@ int main(void) system_clock_config(SYSTEM_CLOCK_FREQ_120MHZ); reset_unreset_blocks_wait(RESETS_BLOCK_IO_BANK0 | RESETS_BLOCK_PADS_BANK0 | RESETS_BLOCK_UART0 | RESETS_BLOCK_TIMER); - gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE); - gpio_init_simple(1, GPIO_FUNC_UART, DISABLE, ENABLE); + gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA); /* UART_TX pin */ + gpio_init(1, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_SCHMITT | GPIO_PAD_IE | GPIO_PAD_OD); /* UART_RX pin */ uart_init(UART_ID_0, &uart_cfg); *(volatile uint32_t *)(WATCHDOG_BASE + 0x2C) = ((1 << 9) | (12 << 0)); timer_start(); - gpio_init_simple(2, GPIO_FUNC_SIO, ENABLE, DISABLE); + gpio_init(2, GPIO_FUNC_NULL | GPIO_PULL_DOWN | GPIO_SCHMITT | GPIO_PAD_IE | GPIO_PAD_OD); /* boot pin */ boot_pin_low = 0; boot_pin_high = 0; - for (uint32_t i = 0; i < 1000; i++) { + for (uint32_t i = 0; i < 10; i++) { if (gpio_read(2)) { boot_pin_high++; } else { diff --git a/example/boot2/src/flash.c b/example/boot2/src/flash.c index 8d01856..f5882f5 100644 --- a/example/boot2/src/flash.c +++ b/example/boot2/src/flash.c @@ -4,20 +4,12 @@ static void flash_cs_force_low(void) { - io_rw_32 *reg; - - /* force QSPI_CS low level as selected */ - reg = (io_rw_32 *)(IO_QSPI_BASE + GPIO_QSPI_CS_CTRL_OFFSET); - *reg = GPIO_OVER_OUT_FORCE_LOW << GPIO_OVER_OUT_POS; + ioqspi_hw->io[1].ctrl = GPIO_OVER_OUT_LOW; } static void flash_cs_force_high(void) { - io_rw_32 *reg; - - /* force QSPI_CS high level as disselected */ - reg = (io_rw_32 *)(IO_QSPI_BASE + GPIO_QSPI_CS_CTRL_OFFSET); - *reg = GPIO_OVER_OUT_FORCE_HIGH << GPIO_OVER_OUT_POS; + ioqspi_hw->io[1].ctrl = GPIO_OVER_OUT_HIGH; } static void flash_put_get(uint8_t *tx, uint8_t *rx, uint32_t count, uint32_t rx_skip) @@ -104,11 +96,11 @@ void flash_enter_quad_xip(uint16_t div) { uint8_t buffer[8]; - pads_qspi_hw->io_qspi_sclk = (GPIO_PADS_DRIVE_STRENGTH_8MA << GPIO_PADS_DRIVE_POS) | (GPIO_PADS_SLEW_RATE_FAST << GPIO_PADS_SLEW_RATE_POS); - pads_qspi_hw_clear->io_qspi_sd0 = 1 << GPIO_PADS_SCHMITT_POS; - pads_qspi_hw_clear->io_qspi_sd1 = 1 << GPIO_PADS_SCHMITT_POS; - pads_qspi_hw_clear->io_qspi_sd2 = 1 << GPIO_PADS_SCHMITT_POS; - pads_qspi_hw_clear->io_qspi_sd3 = 1 << GPIO_PADS_SCHMITT_POS; + pads_qspi_hw->io_qspi_sclk = (GPIO_DRIVE_8MA >> 32) | (GPIO_SLEW_FAST >> 32); + hw_clear_bits(&pads_qspi_hw->io_qspi_sd0, GPIO_SCHMITT >> 32); + hw_clear_bits(&pads_qspi_hw->io_qspi_sd1, GPIO_SCHMITT >> 32); + hw_clear_bits(&pads_qspi_hw->io_qspi_sd2, GPIO_SCHMITT >> 32); + hw_clear_bits(&pads_qspi_hw->io_qspi_sd3, GPIO_SCHMITT >> 32); ssi_hw->ssienr = 0; /* div must be even */ diff --git a/example/peripherals/dma/dma_sniff/main.c b/example/peripherals/dma/dma_sniff/main.c index 93df34a..8165248 100644 --- a/example/peripherals/dma/dma_sniff/main.c +++ b/example/peripherals/dma/dma_sniff/main.c @@ -48,7 +48,7 @@ int main(void) uint32_t sniff_result; reset_unreset_blocks_wait(RESETS_BLOCK_DMA); - gpio_init_simple(0, GPIO_FUNC_UART, DISABLE, ENABLE); + gpio_init(0, GPIO_FUNC_UART | GPIO_PULL_UP | GPIO_DRIVE_4MA); uart_init(UART_ID_0, &uart_cfg); for (int i = 0; i < sizeof(dma_buffer_calc); i++) {