#ifndef __HARDWARE_SSI_REG_H__
#define __HARDWARE_SSI_REG_H__

#include "reg.h"

#define SSI_CTRLR0_TMOD_POS                    (8U)
#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX_MASK   (0x0 << SSI_CTRLR0_TMOD_POS)
#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY_MASK     (0x1 << SSI_CTRLR0_TMOD_POS)
#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY_MASK     (0x2 << SSI_CTRLR0_TMOD_POS)
#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ_MASK (0x3 << SSI_CTRLR0_TMOD_POS)
#define SSI_CTRLR0_DFS_32_POS                  (16U)
#define SSI_CTRLR0_SPI_FRF_POS                 (21U)
#define SSI_CTRLR0_SPI_FRF_VALUE_STD_MASK      (0x0 << SSI_CTRLR0_SPI_FRF_POS)
#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL_MASK     (0x1 << SSI_CTRLR0_SPI_FRF_POS)
#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD_MASK     (0x2 << SSI_CTRLR0_SPI_FRF_POS)

#define SSI_SPI_CTRLR0_TRANS_TYPE_POS             (0U)
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A_MASK (0x0 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A_MASK (0x1 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A_MASK (0x2 << SSI_SPI_CTRLR0_TRANS_TYPE_POS)
#define SSI_SPI_CTRLR0_ADDR_L_POS                 (2U)
#define SSI_SPI_CTRLR0_INST_L_POS                 (8U)
#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE_MASK     (0x0 << SSI_SPI_CTRLR0_INST_L_POS)
#define SSI_SPI_CTRLR0_INST_L_VALUE_4B_MASK       (0x1 << SSI_SPI_CTRLR0_INST_L_POS)
#define SSI_SPI_CTRLR0_INST_L_VALUE_8B_MASK       (0x2 << SSI_SPI_CTRLR0_INST_L_POS)
#define SSI_SPI_CTRLR0_INST_L_VALUE_16_MASKB      (0x3 << SSI_SPI_CTRLR0_INST_L_POS)
#define SSI_SPI_CTRLR0_WAIT_CYCLES_POS            (11U)
#define SSI_SPI_CTRLR0_XIP_CMD_POS                (24U)

#define SSI_SR_BUSY (1 << 0)
#define SSI_SR_TFNF (1 << 1)
#define SSI_SR_TFE  (1 << 2)
#define SSI_SR_RFNE (1 << 3)
#define SSI_SR_RFF  (1 << 4)
#define SSI_SR_TXE  (1 << 5)
#define SSI_SR_DCOL (1 << 6)

typedef struct {
    io_rw_32 ctrlr0;
    io_rw_32 ctrlr1;
    io_rw_32 ssienr;
    io_rw_32 mwcr;
    io_rw_32 ser;
    io_rw_32 baudr;
    io_rw_32 txftlr;
    io_rw_32 rxftlr;
    io_rw_32 txflr;
    io_rw_32 rxflr;
    io_rw_32 sr;
    io_rw_32 imr;
    io_rw_32 isr;
    io_rw_32 risr;
    io_rw_32 txoicr;
    io_rw_32 rxoicr;
    io_rw_32 rxuicr;
    io_rw_32 msticr;
    io_rw_32 icr;
    io_rw_32 dmacr;
    io_rw_32 dmatdlr;
    io_rw_32 dmardlr;
    io_rw_32 idr;
    io_rw_32 ssi_version_id;
    io_rw_32 dr0;
    uint32_t _pad[(0xf0 - 0x60) / 4 - 1];
    io_rw_32 rx_sample_dly;
    io_rw_32 spi_ctrlr0;
    io_rw_32 txd_drive_edge;
} ssi_hw_t;

#define ssi_hw       ((ssi_hw_t *const)XIP_SSI_BASE)
#define ssi_hw_set   ((ssi_hw_t *const)hw_set_alias_untyped(ssi_hw))
#define ssi_hw_clear ((ssi_hw_t *const)hw_clear_alias_untyped(ssi_hw))

#ifdef __cplusplus
extern "C" {
#endif

#ifdef __cplusplus
}
#endif

#endif /* __HARDWARE_SSI_REG_H__ */