#ifndef __HARDWARE_UART_REG_H__ #define __HARDWARE_UART_REG_H__ #define UART_UARTDR_OFFSET (0x000) #define UART_UARTRSR_OFFSET (0x004) #define UART_UARTFR_OFFSET (0x018) #define UART_UARTILPR_OFFSET (0x020) #define UART_UARTIBRD_OFFSET (0x024) #define UART_UARTFBRD_OFFSET (0x028) #define UART_UARTLCR_H_OFFSET (0x02C) #define UART_UARTCR_OFFSET (0x030) #define UART_UARTIFLS_OFFSET (0x034) #define UART_UARTIMSC_OFFSET (0x038) #define UART_UARTRIS_OFFSET (0x03C) #define UART_UARTMIS_OFFSET (0x040) #define UART_UARTICR_OFFSET (0x044) #define UART_UARTDMACR_OFFSET (0x048) #define UART_UARTPERIPHID0_OFFSET (0xFE0) #define UART_UARTPERIPHID1_OFFSET (0xFE4) #define UART_UARTPERIPHID2_OFFSET (0xFE8) #define UART_UARTPERIPHID3_OFFSET (0xFEC) #define UART_UARTPCELLID0 (0xFF0) #define UART_UARTPCELLID1 (0xFF4) #define UART_UARTPCELLID2 (0xFF8) #define UART_UARTPCELLID3 (0xFFC) /* UART_UARTDR_OFFSET @0x000 */ #define UART_UARTDR_DATA_POS (0U) #define UART_UARTDR_DATA_MASK (0xFF << UART_UARTDR_DATA_POS) #define UART_UARTDR_FE (1 << 8U) #define UART_UARTDR_PE (1 << 9U) #define UART_UARTDR_BE (1 << 10U) #define UART_UARTDR_OE (1 << 11U) /* UART_UARTRSR_OFFSET @0x004 */ #define UART_UARTRSR_FE (1 << 0U) #define UART_UARTRSR_PE (1 << 1U) #define UART_UARTRSR_BE (1 << 2U) #define UART_UARTRSR_OE (1 << 3U) /* UART_UARTFR_OFFSET @0x018 */ #define UART_UARTFR_CTS (1 << 0U) #define UART_UARTFR_DSR (1 << 1U) #define UART_UARTFR_DCD (1 << 2U) #define UART_UARTFR_BUSY (1 << 3U) #define UART_UARTFR_RXFE (1 << 4U) #define UART_UARTFR_TXFF (1 << 5U) #define UART_UARTFR_RXFF (1 << 6U) #define UART_UARTFR_TXFE (1 << 7U) #define UART_UARTFR_RI (1 << 8U) /* UART_UARTILPR_OFFSET @0x020 */ #define UART_UARTILPR_ILPDVSR_POS (0U) #define UART_UARTILPR_ILPDVSR_MASK (0xFF << UART_UARTILPR_ILPDVSR_POS) /* UART_UARTIBRD_OFFSET @0x024 */ #define UART_UARTIBRD_BAUD_DIVINT_POS (0U) #define UART_UARTIBRD_BAUD_DIVINT_MASK (0xFFFF << UART_UARTIBRD_BAUD_DIVINT_POS) /* UART_UARTFBRD_OFFSET @0x028 */ #define UART_UARTFBRD_BAUD_DIVFRAC_POS (0U) #define UART_UARTFBRD_BAUD_DIVFRAC_MASK (0x3F << UART_UARTFBRD_BAUD_DIVFRAC_POS) /* UART_UARTLCR_H_OFFSET @0x02C */ #define UART_UARTLCR_H_BRK (1 << 0U) #define UART_UARTLCR_H_PEN (1 << 1U) #define UART_UARTLCR_H_EPS (1 << 2U) #define UART_UARTLCR_H_STP2 (1 << 3U) #define UART_UARTLCR_H_FEN (1 << 4U) #define UART_UARTLCR_H_WLEN_POS (5U) #define UART_UARTLCR_H_WLEN_MASK (0x3 << UART_UARTLCR_H_WLEN_POS) #define UART_UARTLCR_H_SPS (1 << 7U) /* UART_UARTCR_OFFSET @0x030 */ #define UART_UARTCR_UARTEN (1 << 0U) #define UART_UARTCR_SIREN (1 << 1U) #define UART_UARTCR_SIRLP (1 << 2U) #define UART_UARTCR_LBE (1 << 7U) #define UART_UARTCR_TXE (1 << 8U) #define UART_UARTCR_RXE (1 << 9U) #define UART_UARTCR_DTR (1 << 10U) #define UART_UARTCR_RTS (1 << 11U) #define UART_UARTCR_OUT1 (1 << 12U) #define UART_UARTCR_OUT2 (1 << 13U) #define UART_UARTCR_RTSEN (1 << 14U) #define UART_UARTCR_CTSEN (1 << 15U) /* UART_UARTIFLS_OFFSET @0x034 */ #define UART_UARTIFLS_TXIFLSEL_POS (0U) #define UART_UARTIFLS_TXIFLSEL_MASK (0x7 << UART_UARTIFLS_TXIFLSEL_POS) #define UART_UARTIFLS_RXIFLSEL_POS (3U) #define UART_UARTIFLS_RXIFLSEL_MASK (0x7 << UART_UARTIFLS_RXIFLSEL_POS) /* UART_UARTIMSC_OFFSET @0x038 */ #define UART_UARTIMSC_RIMIM (1 << 0U) #define UART_UARTIMSC_CTSMIM (1 << 1U) #define UART_UARTIMSC_DCDMIM (1 << 2U) #define UART_UARTIMSC_DSRMIM (1 << 3U) #define UART_UARTIMSC_RXIM (1 << 4U) #define UART_UARTIMSC_TXIM (1 << 5U) #define UART_UARTIMSC_RTIM (1 << 6U) #define UART_UARTIMSC_FEIM (1 << 7U) #define UART_UARTIMSC_PEIM (1 << 8U) #define UART_UARTIMSC_BEIM (1 << 9U) #define UART_UARTIMSC_OEIM (1 << 10U) /* UART_UARTRIS_OFFSET @0x03C */ #define UART_UARTRIS_RIRMIS (1 << 0U) #define UART_UARTRIS_CTSRMIS (1 << 1U) #define UART_UARTRIS_DCDRMIS (1 << 2U) #define UART_UARTRIS_DSRRMIS (1 << 3U) #define UART_UARTRIS_RXRIS (1 << 4U) #define UART_UARTRIS_TXRIS (1 << 5U) #define UART_UARTRIS_RTRIS (1 << 6U) #define UART_UARTRIS_FERIS (1 << 7U) #define UART_UARTRIS_PERIS (1 << 8U) #define UART_UARTRIS_BERIS (1 << 9U) #define UART_UARTRIS_OERIS (1 << 10U) /* UART_UARTMIS_OFFSET @0x040 */ #define UART_UARTMIS_RIMMIS (1 << 0U) #define UART_UARTMIS_CTSMMIS (1 << 1U) #define UART_UARTMIS_DCDMMIS (1 << 2U) #define UART_UARTMIS_DSRMMIS (1 << 3U) #define UART_UARTMIS_RXMIS (1 << 4U) #define UART_UARTMIS_TXMIS (1 << 5U) #define UART_UARTMIS_RTMIS (1 << 6U) #define UART_UARTMIS_FEMIS (1 << 7U) #define UART_UARTMIS_PEMIS (1 << 8U) #define UART_UARTMIS_BEMIS (1 << 9U) #define UART_UARTMIS_OEMIS (1 << 10U) /* UART_UARTICR_OFFSET @0x044 */ #define UART_UARTICR_RIMIC (1 << 0U) #define UART_UARTICR_CTSMIC (1 << 1U) #define UART_UARTICR_DCDMIC (1 << 2U) #define UART_UARTICR_DSRMIC (1 << 3U) #define UART_UARTICR_RXIC (1 << 4U) #define UART_UARTICR_TXIC (1 << 5U) #define UART_UARTICR_RTIC (1 << 6U) #define UART_UARTICR_FEIC (1 << 7U) #define UART_UARTICR_PEIC (1 << 8U) #define UART_UARTICR_BEIC (1 << 9U) #define UART_UARTICR_OEIC (1 << 10U) /* UART_UARTDMACR_OFFSET @0x048 */ #define UART_UARTDMACR_RXDMAE (1 << 0U) #define UART_UARTDMACR_TXDMAE (1 << 1U) #define UART_UARTDMACR_DMAONERR (1 << 2U) typedef struct { io_rw_32 dr; io_rw_32 rsr; uint32_t _pad0[4]; io_rw_32 fr; uint32_t _pad1; io_rw_32 ilpr; io_rw_32 ibrd; io_rw_32 fbrd; io_rw_32 lcr_h; io_rw_32 cr; io_rw_32 ifls; io_rw_32 imsc; io_rw_32 ris; io_rw_32 mis; io_rw_32 icr; io_rw_32 dmacr; } uart_hw_t; #define uart0_hw ((uart_hw_t *const)UART0_BASE) #define uart1_hw ((uart_hw_t *const)UART1_BASE) #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } #endif #endif /* __HARDWARE_UART_REG_H__ */