#ifndef __HARDWARE_PIO_H__ #define __HARDWARE_PIO_H__ #include "reg.h" #include "pio_reg.h" #include "pio_instr.h" #define PIO0 (0) #define PIO1 (1) #define PIO_MAX (2) #define PIO_SM0 (0) #define PIO_SM1 (1) #define PIO_SM2 (2) #define PIO_SM3 (3) #define PIO_SM_MAX (4) #define PIO_FIFO_DEEPTH (4) #define PIO_SM_COUNT (4) #define PIO_IMEM_SIZE (32) #define PIO_FIFO_JOIN_NONE (0) #define PIO_FIFO_RX_JOIN_TX (1) #define PIO_FIFO_TX_JOIN_RX (2) #define PIO_FIFO_STATUS_SM0_RX_FULL (1 << 0U) #define PIO_FIFO_STATUS_SM1_RX_FULL (1 << 1U) #define PIO_FIFO_STATUS_SM2_RX_FULL (1 << 2U) #define PIO_FIFO_STATUS_SM3_RX_FULL (1 << 3U) #define PIO_FIFO_STATUS_SM0_RX_EMPTY (1 << 8U) #define PIO_FIFO_STATUS_SM1_RX_EMPTY (1 << 9U) #define PIO_FIFO_STATUS_SM2_RX_EMPTY (1 << 10U) #define PIO_FIFO_STATUS_SM3_RX_EMPTY (1 << 11U) #define PIO_FIFO_STATUS_SM0_TX_FULL (1 << 16U) #define PIO_FIFO_STATUS_SM1_TX_FULL (1 << 17U) #define PIO_FIFO_STATUS_SM2_TX_FULL (1 << 18U) #define PIO_FIFO_STATUS_SM3_TX_FULL (1 << 19U) #define PIO_FIFO_STATUS_SM0_TX_EMPTY (1 << 24U) #define PIO_FIFO_STATUS_SM1_TX_EMPTY (1 << 25U) #define PIO_FIFO_STATUS_SM2_TX_EMPTY (1 << 26U) #define PIO_FIFO_STATUS_SM3_TX_EMPTY (1 << 27U) #define PIO_INT_SM0_RX_N_EMPTY (1 << 0) #define PIO_INT_SM1_RX_N_EMPTY (1 << 1) #define PIO_INT_SM2_RX_N_EMPTY (1 << 2) #define PIO_INT_SM3_RX_N_EMPTY (1 << 3) #define PIO_INT_SM0_TX_N_FULL (1 << 4) #define PIO_INT_SM1_TX_N_FULL (1 << 5) #define PIO_INT_SM2_TX_N_FULL (1 << 6) #define PIO_INT_SM3_TX_N_FULL (1 << 7) #define PIO_INT_FLAG_0 (1 << 8) #define PIO_INT_FLAG_1 (1 << 9) #define PIO_INT_FLAG_2 (1 << 10) #define PIO_INT_FLAG_3 (1 << 11) #define PIO_DIR_TX (0) #define PIO_DIR_RX (1) struct pio_cfg_s { uint32_t pio_base; /* pio register address base */ uint16_t clkdiv_int; /* clock divisor of integer part, 1~65535 is available, 0 present 65536 divisor */ uint8_t clkdiv_frac; /* clock divisor of fractional part, (div_frac/256) is actual value */ uint8_t sm; /* state machine identification, 0~3 is available */ uint8_t fifo_join; /* tx/ tx fifo join type */ uint8_t wrap_bottom; /* ater reaching wrap_top, execution is wrapped to this address */ uint8_t wrap_top; /* after reaching this address, execution is wrapped to wrap_bottom */ uint8_t mov_status_sel_rx; /* comparison used for the 'MOV x, STATUS' instruction */ uint8_t mov_status_level; /* comparison level for the 'MOV x, STATUS' instruction */ uint8_t thresh_bits_pull; /* number of bits shifted out of TXSR before autopull or conditional pull, 1~31, 0 present 32 */ uint8_t thresh_bits_push; /* number of bits shifted into RXSR before autopush or conditional push, 1~31, 0 present 32 */ uint8_t out_dir_to_right; /* shift OSR direction */ uint8_t in_dir_to_right; /* shift ISR direction */ uint8_t auto_pull; /* pull automatically when the output shift register is emptied */ uint8_t auto_push; /* push automatically when the input shift register is filled */ uint8_t out_sticky; /* continuously assert the most recent OUT/SET to the pins */ uint8_t inline_outen; /* whether use a bit of OUT data as an auxiliary write enable */ uint8_t outen_sel; /* which data bit to use for inline OUT enable */ uint8_t side_optional; /* allow instructions to perform sideset optionally, rather than on every instruction */ uint8_t side_dest_pindir; /* side data is asserted to pin OEs or pin values */ uint8_t pin_side_count; /* the number of delay bits co-opted for side-set, inclusive of the enable bit, if present */ uint8_t pin_side_base; /* the virtual pin corresponding to SIDESET bit 0, not PEC_PIN_XXX, is absolute pin index */ uint8_t pin_set_count; /* the number of pins asserted by a SET, max of 5 */ uint8_t pin_set_base; /* the virtual pin corresponding to SET bit 0, not PEC_PIN_XXX, is absolute pin index */ uint8_t pin_out_count; /* the number of pins asserted by an OUT, value of 1 to 31 pins, 0 present 32 */ uint8_t pin_out_base; /* the virtual pin corresponding to OUT bit 0 , not PEC_PIN_XXX, is absolute pin index*/ uint8_t pin_in_base; /* the virtual pin corresponding to IN bit 0, not PEC_PIN_XXX, is absolute pin index */ uint8_t pin_jmp; /* the pin index to use as condition for 'JMP PIN' instruction */ }; #ifdef __cplusplus extern "C" { #endif void pio_init(struct pio_cfg_s *cfg); void pio_enable(uint32_t pio_base, uint8_t sm); void pio_disable(uint32_t pio_base, uint8_t sm); void pio_enable_multi(uint32_t pio_base, uint8_t sms); void pio_disable_multi(uint32_t pio_base, uint8_t sms); void pio_restart(uint32_t pio_base, uint8_t sm); void pio_restart_multi(uint32_t pio_base, uint8_t sms); void pio_clkdiv_restart(uint32_t pio_base, uint8_t sm); void pio_clkdiv_restart_multi(uint32_t pio_base, uint8_t sms); uint32_t pio_fifo_get_status(uint32_t pio_base, uint8_t sm); uint8_t pio_fifo_get_tx_level(uint32_t pio_base, uint8_t sm); uint8_t pio_fifo_get_rx_level(uint32_t pio_base, uint8_t sm); void pio_fifo_write(uint32_t pio_base, uint8_t sm, uint32_t value); uint32_t pio_fifo_read(uint32_t pio_base, uint8_t sm); void pio_flag_clear(uint32_t pio_base, uint8_t flag); void pio_flag_set(uint32_t pio_base, uint8_t flag); void pio_flag_clear_multi(uint32_t pio_base, uint8_t flags); void pio_flag_set_multi(uint32_t pio_base, uint8_t flags); uint8_t pio_addr_get(uint32_t pio_base, uint8_t sm); uint16_t pio_instr_get(uint32_t pio_base, uint8_t sm); void pio_instr_insert(uint32_t pio_base, uint8_t sm, uint16_t instr); int pio_instr_is_complete(uint32_t pio_base, uint8_t sm); void pio_instr_place(uint32_t pio_base, uint8_t addr, uint16_t instr); uint32_t pio_int_get_raw_status(uint32_t pio_base); uint32_t pio_int_get_status(uint32_t pio_base, uint8_t int_group); void pio_int_enable(uint32_t pio_base, uint8_t int_group, uint32_t int_type); void pio_int_disable(uint32_t pio_base, uint8_t int_group, uint32_t int_type); void pio_int_force(uint32_t pio_base, uint8_t int_group, uint32_t int_type); void pio_int_deforce(uint32_t pio_base, uint8_t int_group, uint32_t int_type); #ifdef __cplusplus } #endif #endif /* __HARDWARE_PIO_H__ */