#ifndef __HARDWARE_DMA_REG_H__ #define __HARDWARE_DMA_REG_H__ #define DMA_CH0_READ_ADDR_OFFSET (0x000) #define DMA_CH0_WRITE_ADDR_OFFSET (0x004) #define DMA_CH0_TRANS_COUNT_OFFSET (0x008) #define DMA_CH0_CTRL_TRIG_OFFSET (0x00C) #define DMA_CH1_READ_ADDR_OFFSET (0x040) #define DMA_CH1_WRITE_ADDR_OFFSET (0x044) #define DMA_CH1_TRANS_COUNT_OFFSET (0x048) #define DMA_CH1_CTRL_TRIG_OFFSET (0x04C) #define DMA_INTR_OFFSET (0x400) #define DMA_INTE0_OFFSET (0x404) #define DMA_INTF0_OFFSET (0x408) #define DMA_INTS0_OFFSET (0x40C) #define DMA_INTE1_OFFSET (0x414) #define DMA_INTF1_OFFSET (0x418) #define DMA_INTS1_OFFSET (0x41C) #define DMA_TIMER0_OFFSET (0x420) #define DMA_TIMER1_OFFSET (0x424) #define DMA_TIMER2_OFFSET (0x428) #define DMA_TIMER3_OFFSET (0x42C) #define DMA_MULTI_CHAN_TRIGGER_OFFSET (0x430) #define DMA_SNIFF_CTRL_OFFSET (0x434) #define DMA_SNIFF_DATA_OFFSET (0x438) #define DMA_FIFO_LEVELS_OFFSET (0x440) #define DMA_CHAN_ABORT_OFFSET (0x444) #define DMA_N_CHANNELS_OFFSET (0x448) /* DMA_CHx_CTRL_TRIG_OFFSET @0x00C */ #define DMA_CTRL_EN (1 << 0U) #define DMA_CTRL_HIGH_PRIORITY (1 << 0U) #define DMA_CTRL_DATA_SIZE_POS (2U) #define DMA_CTRL_DATA_SIZE_MASK (0x3 << DMA_CTRL_DATA_SIZE_POS) #define DMA_CTRL_INCR_READ (1 << 4U) #define DMA_CTRL_INCR_WRITE (1 << 5U) #define DMA_CTRL_RING_SIZE_POS (6U) #define DMA_CTRL_RING_SIZE_MASK (0xF << DMA_CTRL_RING_SIZE_POS) #define DMA_CTRL_RING_SEL_WRITE (1 << 10U) #define DMA_CTRL_CHAIN_TO_POS (11U) #define DMA_CTRL_CHAIN_TO_MASK (0xF << DMA_CTRL_CHAIN_TO_POS) #define DMA_CTRL_TREQ_SEL_POS (15U) #define DMA_CTRL_TREQ_SEL_MASK (0x3F << DMA_CTRL_TREQ_SEL_POS) #define DMA_CTRL_IRQ_QUIET (1 << 21U) #define DMA_CTRL_BSWAP (1 << 22U) #define DMA_CTRL_SNIFF_EN (1 << 23U) #define DMA_CTRL_BUSY (1 << 24U) #define DMA_CTRL_WRITE_ERROR (1 << 29U) #define DMA_CTRL_READ_ERROR (1 << 30U) #define DMA_CTRL_AHB_ERROR (1 << 31U) /* DMA_TIMERx_OFFSET @0x420/0x424/0x428/0x42C */ #define DMA_TIMER_Y_POS (0U) #define DMA_TIMER_Y_MASK (0xFFFF << DMA_TIMER_Y_POS) #define DMA_TIMER_X_POS (16U) #define DMA_TIMER_X_MASK (0xFFFF << DMA_TIMER_X_POS) /* DMA_SNIFF_CTRL_OFFSET @0x434 */ #define DMA_SNIFF_EN (1 << 0U) #define DMA_SNIFF_DMACH_POS (1U) #define DMA_SNIFF_DMACH_MASK (0xF << DMA_SNIFF_DMACH_POS) #define DMA_SNIFF_CALC_POS (5U) #define DMA_SNIFF_CALC_MASK (0xF << DMA_SNIFF_CALC_POS) #define DMA_SNIFF_BSWAP (1 << 9U) #define DMA_SNIFF_OUT_REV (1 << 10U) #define DMA_SNIFF_OUT_INV (1 << 11U) /* DMA_FIFO_LEVELS_OFFSET @0x440 */ #define DMA_TDF_LVL_POS (0U) #define DMA_TDF_LVL_MASK (0xFF << DMA_TDF_LVL_POS) #define DMA_TAF_LVL_POS (8U) #define DMA_TAF_LVL_MASK (0xFF << DMA_TAF_LVL_POS) #define DMA_RAF_LVL_POS (16U) #define DMA_RAF_LVL_MASK (0xFF << DMA_RAF_LVL_POS) #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } #endif #endif /* __HARDWARE_DMA_REG_H__ */