ENTRY(isr_reset)

MEMORY
{
    FLASH (rx)       :ORIGIN = 0x10010000, LENGTH = 4M - 64K
    RAM (xrw)        :ORIGIN = 0x20000000, LENGTH = 256K
}

_stack_top = 0x20040000 + 4 * 1024;
_stack_top_core1 = 0x20041000 + 4 * 1024;

PHDRS
{
    fw_header PT_LOAD FLAGS(6); /* R + X */
    isr_reset PT_LOAD FLAGS(6); /* R + X */
    text PT_LOAD FLAGS(5);      /* R + X */
    rodata PT_LOAD FLAGS(6);    /* R + W */
    shell PT_LOAD FLAGS(6);     /* R + W */
    data PT_LOAD FLAGS(6);      /* R + W */
    bss PT_LOAD FLAGS(6);       /* R + W */
}

SECTIONS
{
    .fw_header :
    {
        . = ALIGN(4);
        KEEP(*(.fw_header))
        . = ALIGN(4);
    } >FLASH :fw_header

    .isr_reset :
    {
        . = ALIGN(4);
        KEEP(*(.text.isr_reset))
        . = ALIGN(4);
    } >FLASH :isr_reset

    .text :
    {
        . = ALIGN(4);
        *(*.text*)
        . = ALIGN(4);
    } >FLASH :text

    .rodata :
    {
        . = ALIGN(4);
        *(*.rodata*)
        . = ALIGN(4);
    } >FLASH :rodata

    .shell :
    {
        . = ALIGN(4);
        __fsymtab_start = .;
        KEEP(*(FSymTab))
        __fsymtab_end = .;

        . = ALIGN(4);
        __vsymtab_start = .;
        KEEP(*(VSymTab))
        __vsymtab_end = .;
    } >FLASH :shell

    .data :
    {
        . = ALIGN(4);
        _data_load = LOADADDR(.data);
        _data_run = .;
        *(*.data*)
        . = ALIGN(4);
        _data_run_end = .;
    } >RAM AT>FLASH :data

    .bss (NOLOAD) :
    {
        . = ALIGN(4);
        _bss_run = .;
        *(*.bss*)
        . = ALIGN(4);
        _bss_run_end = .;
    } >RAM :bss
}