#ifndef __HARDWARE_CLOCK_REG_H__ #define __HARDWARE_CLOCK_REG_H__ /* ROSC_BASE @0x40060000 */ #define CLOCK_ROSC_CTRL_OFFSET (0x000) #define CLOCK_ROSC_FREQA_OFFSET (0x004) #define CLOCK_ROSC_FREQB_OFFSET (0x008) #define CLOCK_ROSC_DORMANT_OFFSET (0x00C) #define CLOCK_ROSC_DIV_OFFSET (0x010) #define CLOCK_ROSC_PHASE_OFFSET (0x014) #define CLOCK_ROSC_STATUS_OFFSET (0x018) #define CLOCK_ROSC_RANDOMBIT_OFFSET (0x01C) #define CLOCK_ROSC_COUNT_OFFSET (0x020) /* XOSC_BASE @0x40024000 */ #define CLOCK_XOSC_CTRL_OFFSET (0x000) #define CLOCK_XOSC_STATUS_OFFSET (0x004) #define CLOCK_XOSC_DORMANT_OFFSET (0x008) #define CLOCK_XOSC_STARTUP_OFFSET (0x00C) #define CLOCK_XOSC_COUNT_OFFSET (0x01C) /* PLL_SYS_BASE @0x40028000 */ /* PLL_USB_BASE @0x4002C000 */ #define CLOCK_PLL_CS_OFFSET (0x000) #define CLOCK_PLL_PWR_OFFSET (0x004) #define CLOCK_PLL_FBDIV_INT_OFFSET (0x008) #define CLOCK_PLL_PRIM_OFFSET (0x00C) /* CLOCKS_BASE @0x40008000 */ #define CLOCK_CTRL_OFFSET (0x000) #define CLOCK_DIV_OFFSET (0x004) #define CLOCK_SELECTED_OFFSET (0x008) #define CLOCK_GPOUT0_CTRL_OFFSET (0x000) #define CLOCK_GPOUT0_DIV_OFFSET (0x004) #define CLOCK_GPOUT0_SELECTED_OFFSET (0x008) #define CLOCK_GPOUT1_CTRL_OFFSET (0x00C) #define CLOCK_GPOUT1_DIV_OFFSET (0x010) #define CLOCK_GPOUT1_SELECTED_OFFSET (0x014) #define CLOCK_GPOUT2_CTRL_OFFSET (0x018) #define CLOCK_GPOUT2_DIV_OFFSET (0x01C) #define CLOCK_GPOUT2_SELECTED_OFFSET (0x020) #define CLOCK_GPOUT3_CTRL_OFFSET (0x024) #define CLOCK_GPOUT3_DIV_OFFSET (0x028) #define CLOCK_GPOUT3_SELECTED_OFFSET (0x02C) #define CLOCK_REF_CTRL_OFFSET (0x030) #define CLOCK_REF_DIV_OFFSET (0x034) #define CLOCK_REF_SELECTED_OFFSET (0x038) #define CLOCK_SYS_CTRL_OFFSET (0x03C) #define CLOCK_SYS_DIV_OFFSET (0x040) #define CLOCK_SYS_SELECTED_OFFSET (0x044) #define CLOCK_PERI_CTRL_OFFSET (0x048) #define CLOCK_PERI_DIV_OFFSET (0x04C) #define CLOCK_PERI_SELECTED_OFFSET (0x050) #define CLOCK_USB_CTRL_OFFSET (0x054) #define CLOCK_USB_DIV_OFFSET (0x058) #define CLOCK_USB_SELECTED_OFFSET (0x05C) #define CLOCK_ADC_CTRL_OFFSET (0x060) #define CLOCK_ADC_DIV_OFFSET (0x064) #define CLOCK_ADC_SELECTED_OFFSET (0x068) #define CLOCK_RTC_CTRL_OFFSET (0x06C) #define CLOCK_RTC_DIV_OFFSET (0x070) #define CLOCK_RTC_SELECTED_OFFSET (0x074) /* CLOCK_ROSC_CTRL_OFFSET */ #define CLOCK_ROSC_FREQ_RANGE_POS (0) #define CLOCK_ROSC_FREQ_RANGE_MASK (0xFFF) #define CLOCK_ROSC_ENABLE_POS (12) #define CLOCK_ROSC_ENABLE_MASK (0xFFF) /* CLOCK_ROSC_FREQ_OFFSET */ #define CLOCK_ROSC_STRENGTH_MASK (0x7) /* CLOCK_XOSC_CTRL_OFFSET */ #define CLOCK_XOSC_FREQ_RANGE_POS (0) #define CLOCK_XOSC_FREQ_RANGE_MASK (0xFFF) #define CLOCK_XOSC_ENABLE_POS (12) #define CLOCK_XOSC_ENABLE_MASK (0xFFF) /* CLOCK_XOSC_STARTUP_OFFSET */ #define CLOCK_XOSC_STARTUP_DELAY_POS (0) #define CLOCK_XOSC_STARTUP_DELAY_MASK (0x3FFF) #define CLOCK_XOSC_STARTUP_X4_POS (20) /* CLOCK_PLL_CS_OFFSET @ 0x000 */ #define CLOCK_PLL_CS_REFDIV_POS (0) #define CLOCK_PLL_CS_REFDIV_MASK (0x3F << CLOCK_PLL_CS_REFDIV_POS) #define CLOCK_PLL_CS_BYPASS (1 << 8U) #define CLOCK_PLL_CS_LOCK (1 << 31U) /* CLOCK_PLL_PWR_OFFSET @ 0x004 */ #define CLOCK_PLL_PWR_PD (1 << 0U) #define CLOCK_PLL_PWR_DSMPD (1 << 2U) #define CLOCK_PLL_PWR_POSTDIVPD (1 << 3U) #define CLOCK_PLL_PWR_VCOPD (1 << 5U) /* CLOCK_PLL_PRIM_OFFSET @ 0x00C */ #define CLOCK_PLL_PRIM_POSTDIV2_POS (12U) #define CLOCK_PLL_PRIM_POSTDIV2_MASK (0x7 << CLOCK_PLL_PRIM_POSTDIV2_POS) #define CLOCK_PLL_PRIM_POSTDIV1_POS (16U) #define CLOCK_PLL_PRIM_POSTDIV1_MASK (0x7 << CLOCK_PLL_PRIM_POSTDIV1_POS) /* CLOCK_CTRL_OFFSET @ 0x000 */ #define CLOCK_CTRL_SRC_POS (0U) #define CLOCK_CTRL_SRC_MASK (0xF << CLOCK_CTRL_SRC_POS) #define CLOCK_CTRL_AUXSRC_POS (5U) #define CLOCK_CTRL_AUXSRC_MASK (0xF << CLOCK_CTRL_AUXSRC_POS) #define CLOCK_CTRL_KILL (1 << 10U) #define CLOCK_CTRL_ENABLE (1 << 11U) #define CLOCK_CTRL_DC50 (1 << 12U) #define CLOCK_CTRL_PHASE_POS (16U) #define CLOCK_CTRL_NUDGE (1 << 20U) /* CLOCK_DIV_OFFSET @0x004 */ #define CLOCK_DIV_FRAC_POS (0U) #define CLOCK_DIV_INT_POS (8U) typedef struct { io_rw_32 ctrl; io_rw_32 div; io_rw_32 selected; } clock_hw_t; typedef struct { io_rw_32 ref_khz; io_rw_32 min_khz; io_rw_32 max_khz; io_rw_32 delay; io_rw_32 interval; io_rw_32 src; io_ro_32 status; io_ro_32 result; } fc_hw_t; typedef struct { clock_hw_t clk[10]; struct { io_rw_32 ctrl; io_rw_32 status; } resus; fc_hw_t fc0; io_rw_32 wake_en0; io_rw_32 wake_en1; io_rw_32 sleep_en0; io_rw_32 sleep_en1; io_rw_32 enabled0; io_rw_32 enabled1; io_rw_32 intr; io_rw_32 inte; io_rw_32 intf; io_rw_32 ints; } clocks_hw_t; #define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) typedef struct { io_rw_32 cs; io_rw_32 pwr; io_rw_32 fbdiv_int; io_rw_32 prim; } pll_hw_t; #define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE) #define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE) typedef struct { io_rw_32 ctrl; io_rw_32 freqa; io_rw_32 freqb; io_rw_32 dormant; io_rw_32 div; io_rw_32 phase; io_rw_32 status; io_rw_32 randombit; io_rw_32 count; io_rw_32 dftx; } rosc_hw_t; #define rosc_hw ((rosc_hw_t *const)ROSC_BASE) typedef struct { io_rw_32 ctrl; io_rw_32 status; io_rw_32 dormant; io_rw_32 startup; io_rw_32 _reserved[3]; io_rw_32 count; } xosc_hw_t; #define xosc_hw ((xosc_hw_t *const)XOSC_BASE) #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } #endif #endif /* __HARDWARE_CLOCK_REG_H__ */