#ifndef __HARDWARE_DMA_H__ #define __HARDWARE_DMA_H__ #include "reg.h" #include "dma_reg.h" #define DMA_CHANNEL_0 (0) #define DMA_CHANNEL_1 (1) #define DMA_CHANNEL_2 (2) #define DMA_CHANNEL_3 (3) #define DMA_CHANNEL_4 (4) #define DMA_CHANNEL_5 (5) #define DMA_CHANNEL_6 (6) #define DMA_CHANNEL_7 (7) #define DMA_CHANNEL_8 (8) #define DMA_CHANNEL_9 (9) #define DMA_CHANNEL_10 (10) #define DMA_CHANNEL_11 (11) #define DMA_CHANNEL_MAX (12) #define DMA_CHANNEL_MASK ((1 << DMA_CHANNEL_MAX) - 1) #define DMA_INT_GROUP_0 (0) #define DMA_INT_GROUP_1 (1) #define DMA_REQ_PIO0_TX0 (0) #define DMA_REQ_PIO0_TX1 (1) #define DMA_REQ_PIO0_TX2 (2) #define DMA_REQ_PIO0_TX3 (3) #define DMA_REQ_PIO0_RX0 (4) #define DMA_REQ_PIO0_RX1 (5) #define DMA_REQ_PIO0_RX2 (6) #define DMA_REQ_PIO0_RX3 (7) #define DMA_REQ_PIO1_TX0 (8) #define DMA_REQ_PIO1_TX1 (9) #define DMA_REQ_PIO1_TX2 (10) #define DMA_REQ_PIO1_TX3 (11) #define DMA_REQ_PIO1_RX0 (12) #define DMA_REQ_PIO1_RX1 (13) #define DMA_REQ_PIO1_RX2 (14) #define DMA_REQ_PIO1_RX3 (15) #define DMA_REQ_SPI0_TX (16) #define DMA_REQ_SPI0_RX (17) #define DMA_REQ_SPI1_TX (18) #define DMA_REQ_SPI1_RX (19) #define DMA_REQ_UART0_TX (20) #define DMA_REQ_UART0_RX (21) #define DMA_REQ_UART1_TX (22) #define DMA_REQ_UART1_RX (23) #define DMA_REQ_PWM_WRAP0 (24) #define DMA_REQ_PWM_WRAP1 (25) #define DMA_REQ_PWM_WRAP2 (26) #define DMA_REQ_PWM_WRAP3 (27) #define DMA_REQ_PWM_WRAP4 (28) #define DMA_REQ_PWM_WRAP5 (29) #define DMA_REQ_PWM_WRAP6 (30) #define DMA_REQ_PWM_WRAP7 (31) #define DMA_REQ_I2C0_TX (32) #define DMA_REQ_I2C0_RX (33) #define DMA_REQ_I2C1_TX (34) #define DMA_REQ_I2C1_RX (35) #define DMA_REQ_ADC (36) #define DMA_REQ_XIP_STREAM (37) #define DMA_REQ_XIP_SSITX (38) #define DMA_REQ_XIP_SSIRX (39) #define DMA_REQ_TIMER_0 (0x3B) #define DMA_REQ_TIMER_1 (0x3C) #define DMA_REQ_TIMER_2 (0x3D) #define DMA_REQ_TIMER_3 (0x3E) #define DMA_REQ_FOREVER (0x3F) #define DMA_DATA_SIZE_8BIT (0) #define DMA_DATA_SIZE_16BIT (1) #define DMA_DATA_SIZE_32BIT (2) #define DMA_RING_SIZE_NONE (0) #define DMA_RING_SIZE_2B (1) #define DMA_RING_SIZE_4B (2) #define DMA_RING_SIZE_8B (3) #define DMA_RING_SIZE_16B (4) #define DMA_RING_SIZE_32B (5) #define DMA_RING_SIZE_64B (6) #define DMA_RING_SIZE_128B (7) #define DMA_RING_SIZE_256B (8) #define DMA_RING_SIZE_512B (9) #define DMA_RING_SIZE_1kB (10) #define DMA_RING_SIZE_2kB (11) #define DMA_RING_SIZE_4kB (12) #define DMA_RING_SIZE_8kB (13) #define DMA_RING_SIZE_16kB (14) #define DMA_RING_SIZE_32kB (15) #define DMA_SNIFF_CALC_CRC32 (0) #define DMA_SNIFF_CALC_CRC32_BITREV (1) #define DMA_SNIFF_CALC_CRC16_CCITT (2) #define DMA_SNIFF_CALC_CRC16_CCITT_BITREV (3) #define DMA_SNIFF_CALC_EVEN_CHECKSUM (14) #define DMA_SNIFF_CALC_SUM32 (15) union dma_ctrl_s { struct { uint32_t en : 1; /* [ 0], r/w */ uint32_t high_priority : 1; /* [ 1], r/w */ uint32_t data_size : 2; /* [ 3: 2], r/w */ uint32_t incr_read : 1; /* [ 4], r/w */ uint32_t incr_write : 1; /* [ 5], r/w */ uint32_t ring_size : 4; /* [ 9: 6], r/w */ uint32_t ring_sel_write : 1; /* [ 10], r/w */ uint32_t chain_to : 4; /* [14:11], r/w */ uint32_t request : 6; /* [20:15], r/w */ uint32_t irq_quiet : 1; /* [ 21], r/w */ uint32_t byte_swap : 1; /* [ 22], r/w */ uint32_t sniff_en : 1; /* [ 23], r/w */ uint32_t busy : 1; /* [ 24], ro */ uint32_t reserved : 4; /* [28:25], reserved */ uint32_t error_write : 1; /* [ 29], wc */ uint32_t error_read : 1; /* [ 30], wc */ uint32_t error_ahb : 1; /* [ 31], ro */ } bits; uint32_t word; }; struct dma_cfg_s { uint32_t read_addr; uint32_t write_addr; uint32_t trans_count; // union dma_ctrl_s ctrl; uint8_t channel; uint8_t request; uint8_t data_size; uint8_t incr_read; uint8_t incr_write; uint8_t irq_quiet; uint8_t byte_swap; uint8_t chain_to; uint8_t high_priority; uint8_t ring_sel_write; uint8_t ring_size; uint8_t sniff_en; }; struct dma_sniff_cfg_s { uint8_t channel; uint8_t calc; uint8_t byte_swap; uint8_t out_rev; /* bit = ~bit */ uint8_t out_inv; /* bit31-0 -> bit0-31 */ }; #ifdef __cplusplus extern "C" { #endif void dma_init(struct dma_cfg_s *cfg); void dma_enable_and_trig(uint8_t ch); void dma_disable(uint8_t ch); void dma_trig_multi(uint16_t chs); void dma_abort_multi(uint16_t chs); void dma_read_addr_update(uint8_t ch, uint32_t addr); void dma_write_addr_update(uint8_t ch, uint32_t addr); void dma_trans_count_update(uint8_t ch, uint8_t count); uint32_t dma_trans_count_remain_get(uint8_t ch); void dma_timer_set(uint8_t ch, uint16_t x, uint16_t y); void dma_sniff_init(struct dma_sniff_cfg_s *cfg); void dma_sniff_enable(void); void dma_sniff_disable(void); void dma_sniff_write(uint32_t seed); uint32_t dma_sniff_read(void); uint32_t dma_int_get_raw_status(void); void dma_int_clear_raw_status(uint32_t chs); uint32_t dma_int_get_status(uint8_t int_group); void dma_int_clear(uint8_t group, uint32_t chs); void dma_int_enable(uint8_t int_group, uint32_t chs); void dma_int_disable(uint8_t int_group, uint32_t chs); void dma_int_force(uint8_t int_group, uint32_t chs); void dma_int_deforce(uint8_t int_group, uint32_t chs); #ifdef __cplusplus } #endif #endif /* __HARDWARE_DMA_H__ */