#ifndef __HARDWARE_M0PLUS_REG_H__
#define __HARDWARE_M0PLUS_REG_H__

#include "reg.h"

/* Nested Vectored Interrupt Controller(NVIC) */
#define M0PLUS_NVIC_ISER_OFFSET 0x0000E100
#define M0PLUS_NVIC_ICER_OFFSET 0x0000E180
#define M0PLUS_NVIC_ISPR_OFFSET 0x0000E200
#define M0PLUS_NVIC_ICPR_OFFSET 0x0000E280
#define M0PLUS_NVIC_IPR0_OFFSET 0x0000E400

/* System Control Block(SCB) */
#define M0PLUS_CPUID_OFFSET 0x0000ED00
#define M0PLUS_ICSR_OFFSET  0x0000ED04
#define M0PLUS_VTOR_OFFSET  0x0000ED08
#define M0PLUS_AIRCR_OFFSET 0x0000ED0C
#define M0PLUS_SCR_OFFSET   0x0000ED10
#define M0PLUS_CCR_OFFSET   0x0000ED14
#define M0PLUS_SHPR2_OFFSET 0x0000ED1C
#define M0PLUS_SHPR3_OFFSET 0x0000ED20

#ifdef __cplusplus
extern "C" {
#endif

#ifdef __cplusplus
}
#endif

#endif /* __HARDWARE_M0PLUS_REG_H__ */