#ifndef __HARDWARE_GPIO_REG_H__
#define __HARDWARE_GPIO_REG_H__

/* IO_BANK0_BASE @0x40014000 */
#define GPIO_STATUS_OFFSET            (0x000)
#define GPIO_CTRL_OFFSET              (0x004)
#define GPIO_INTR_OFFSET              (0x0F0) /* raw interrupts */
#define GPIO_INTE_PROC0_OFFSET        (0x100) /* interrupt enable for proc0 */
#define GPIO_INTF_PROC0_OFFSET        (0x110) /* interrupt force for proc0 */
#define GPIO_INTS_PROC0_OFFSET        (0x120) /* interrupt status after masking & forcing for proc0 */
#define GPIO_INTE_PROC1_OFFSET        (0x130) /* interrupt enable for proc1 */
#define GPIO_INTF_PROC1_OFFSET        (0x140) /* interrupt force for proc1 */
#define GPIO_INTS_PROC1_OFFSET        (0x150) /* interrupt status after masking & forcing for proc1 */
#define GPIO_INTE_DORMANT_WAKE_OFFSET (0x160) /* interrupt enable for dormant_wake */
#define GPIO_INTF_DORMANT_WAKE_OFFSET (0x170) /* interrupt force for dormant_wake */
#define GPIO_INTS_DORMANT_WAKE_OFFSET (0x180) /* interrupt status after masking & forcing for dormant_wake */

/* GPIO_STATUS_OFFSET */
#define GPIO_STATUS_OE_FROM_PERI (1 << 12)
#define GPIO_STATUS_OE_TO_PAD    (1 << 13)
#define GPIO_STATUS_IN_FROM_PAD  (1 << 17)
#define GPIO_STATUS_IN_TO_PERI   (1 << 19)
#define GPIO_STATUS_IRQ_FROM_PAD (1 << 24)
#define GPIO_STATUS_IRQ_TO_PROC  (1 << 26)

typedef struct {
    io_rw_32 voltage_select;
    io_rw_32 io[30];
} pads_bank0_hw_t;

#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE)

typedef struct {
    io_rw_32 voltage_select;
    io_rw_32 io_qspi_sclk;
    io_rw_32 io_qspi_sd0;
    io_rw_32 io_qspi_sd1;
    io_rw_32 io_qspi_sd2;
    io_rw_32 io_qspi_sd3;
    io_rw_32 io_qspi_ss;
} pads_qspi_hw_t;

#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE)

typedef struct {
    io_rw_32 inte[4];
    io_rw_32 intf[4];
    io_rw_32 ints[4];
} io_irq_ctrl_hw_t;

typedef struct {
    struct {
        io_rw_32 status;
        io_rw_32 ctrl;
    } io[30];
    io_rw_32 intr[4];
    io_irq_ctrl_hw_t proc0_irq_ctrl;
    io_irq_ctrl_hw_t proc1_irq_ctrl;
    io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
} iobank0_hw_t;

#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE)

typedef struct {
    struct {
        io_rw_32 status;
        io_rw_32 ctrl;
    } io[6];
} ioqspi_hw_t;

#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE)

#ifdef __cplusplus
extern "C" {
#endif

#ifdef __cplusplus
}
#endif

#endif /* __HARDWARE_GPIO_REG_H__ */