#ifndef __HARDWARE_PIO_REG_H__ #define __HARDWARE_PIO_REG_H__ #define PIO_CTRL_OFFSET (0x000) /* PIO control register */ #define PIO_FSTAT_OFFSET (0x004) /* FIFO status register */ #define PIO_FDEBUG_OFFSET (0x008) /* FIFO debug register */ #define PIO_FLEVEL_OFFSET (0x00C) /* FIFO levels */ #define PIO_TXF0_OFFSET (0x010) /* Direct write access to the TX FIFO for state machine 0 */ #define PIO_TXF1_OFFSET (0x014) /* Direct write access to the TX FIFO for state machine 1 */ #define PIO_TXF2_OFFSET (0x018) /* Direct write access to the TX FIFO for state machine 2 */ #define PIO_TXF3_OFFSET (0x01C) /* Direct write access to the TX FIFO for state machine 3 */ #define PIO_RXF0_OFFSET (0x020) /* Direct read access to the RX FIFO for state machine 0 */ #define PIO_RXF1_OFFSET (0x024) /* Direct read access to the RX FIFO for state machine 1 */ #define PIO_RXF2_OFFSET (0x028) /* Direct read access to the RX FIFO for state machine 2 */ #define PIO_RXF3_OFFSET (0x02C) /* Direct read access to the RX FIFO for state machine 3 */ #define PIO_IRQ_OFFSET (0x030) /* State machine IRQ flags register */ #define PIO_IRQ_FORCE_OFFSET (0x034) /* Writing a 1 to each of these bits will forcibly assert the corresponding IRQ */ #define PIO_INPUT_SYNC_BYPASS_OFFSET (0x038) /* There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities */ #define PIO_DBG_PADOUT_OFFSET (0x03C) /* Read to sample the pad output values PIO is currently driving to the GPIOs */ #define PIO_DBG_PADOE_OFFSET (0x040) /* Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs */ #define PIO_DBG_CFGINFO_OFFSET (0x044) /* The PIO hardware has some free parameters that may vary between chip products */ #define PIO_INSTR_MEM0_OFFSET (0x048) /* Write-only access to instruction memory location 0 */ #define PIO_INSTR_MEM1_OFFSET (0x04C) /* Write-only access to instruction memory location 1 */ #define PIO_INSTR_MEM2_OFFSET (0x050) /* Write-only access to instruction memory location 2 */ #define PIO_INSTR_MEM3_OFFSET (0x054) /* Write-only access to instruction memory location 3 */ #define PIO_INSTR_MEM4_OFFSET (0x058) /* Write-only access to instruction memory location 4 */ #define PIO_INSTR_MEM5_OFFSET (0x05C) /* Write-only access to instruction memory location 5 */ #define PIO_INSTR_MEM6_OFFSET (0x060) /* Write-only access to instruction memory location 6 */ #define PIO_INSTR_MEM7_OFFSET (0x064) /* Write-only access to instruction memory location 7 */ #define PIO_INSTR_MEM8_OFFSET (0x068) /* Write-only access to instruction memory location 8 */ #define PIO_INSTR_MEM9_OFFSET (0x06C) /* Write-only access to instruction memory location 9 */ #define PIO_INSTR_MEM10_OFFSET (0x070) /* Write-only access to instruction memory location 10 */ #define PIO_INSTR_MEM11_OFFSET (0x074) /* Write-only access to instruction memory location 11 */ #define PIO_INSTR_MEM12_OFFSET (0x078) /* Write-only access to instruction memory location 12 */ #define PIO_INSTR_MEM13_OFFSET (0x07C) /* Write-only access to instruction memory location 13 */ #define PIO_INSTR_MEM14_OFFSET (0x080) /* Write-only access to instruction memory location 14 */ #define PIO_INSTR_MEM15_OFFSET (0x084) /* Write-only access to instruction memory location 15 */ #define PIO_INSTR_MEM16_OFFSET (0x088) /* Write-only access to instruction memory location 16 */ #define PIO_INSTR_MEM17_OFFSET (0x08C) /* Write-only access to instruction memory location 17 */ #define PIO_INSTR_MEM18_OFFSET (0x090) /* Write-only access to instruction memory location 18 */ #define PIO_INSTR_MEM19_OFFSET (0x094) /* Write-only access to instruction memory location 19 */ #define PIO_INSTR_MEM20_OFFSET (0x098) /* Write-only access to instruction memory location 20 */ #define PIO_INSTR_MEM21_OFFSET (0x09C) /* Write-only access to instruction memory location 21 */ #define PIO_INSTR_MEM22_OFFSET (0x0A0) /* Write-only access to instruction memory location 22 */ #define PIO_INSTR_MEM23_OFFSET (0x0A4) /* Write-only access to instruction memory location 23 */ #define PIO_INSTR_MEM24_OFFSET (0x0A8) /* Write-only access to instruction memory location 24 */ #define PIO_INSTR_MEM25_OFFSET (0x0AC) /* Write-only access to instruction memory location 25 */ #define PIO_INSTR_MEM26_OFFSET (0x0B0) /* Write-only access to instruction memory location 26 */ #define PIO_INSTR_MEM27_OFFSET (0x0B4) /* Write-only access to instruction memory location 27 */ #define PIO_INSTR_MEM28_OFFSET (0x0B8) /* Write-only access to instruction memory location 28 */ #define PIO_INSTR_MEM29_OFFSET (0x0BC) /* Write-only access to instruction memory location 29 */ #define PIO_INSTR_MEM30_OFFSET (0x0C0) /* Write-only access to instruction memory location 30 */ #define PIO_INSTR_MEM31_OFFSET (0x0C4) /* Write-only access to instruction memory location 31 */ #define PIO_SM0_CLKDIV_OFFSET (0x0C8) /* Clock divisor register for state machine 0 */ #define PIO_SM0_EXECCTRL_OFFSET (0x0CC) /* Execution/behavioural settings for state machine 0 */ #define PIO_SM0_SHIFTCTRL_OFFSET (0x0D0) /* Control behaviour of the input/output shift registers for state machine 0 */ #define PIO_SM0_ADDR_OFFSET (0x0D4) /* Current instruction address of state machine 0 */ #define PIO_SM0_INSTR_OFFSET (0x0D8) /* Instruction currently addressed by state machine or execute an instruction immediately */ #define PIO_SM0_PINCTRL_OFFSET (0x0DC) /* State machine pin control */ #define PIO_SM1_CLKDIV_OFFSET (0x0E0) /* Clock divisor register for state machine 1 */ #define PIO_SM1_EXECCTRL_OFFSET (0x0E4) /* Execution/behavioural settings for state machine 1 */ #define PIO_SM1_SHIFTCTRL_OFFSET (0x0E8) /* Control behaviour of the input/output shift registers for state machine 1 */ #define PIO_SM1_ADDR_OFFSET (0x0EC) /* Current instruction address of state machine 1 */ #define PIO_SM1_INSTR_OFFSET (0x0F0) /* Instruction currently addressed by state machine or execute an instruction immediately */ #define PIO_SM1_PINCTRL_OFFSET (0x0F4) /* State machine pin control */ #define PIO_SM2_CLKDIV_OFFSET (0x0F8) /* Clock divisor register for state machine 2 */ #define PIO_SM2_EXECCTRL_OFFSET (0x0FC) /* Execution/behavioural settings for state machine 2 */ #define PIO_SM2_SHIFTCTRL_OFFSET (0x100) /* Control behaviour of the input/output shift registers for state machine 2 */ #define PIO_SM2_ADDR_OFFSET (0x104) /* Current instruction address of state machine 2 */ #define PIO_SM2_INSTR_OFFSET (0x108) /* Instruction currently addressed by state machine or execute an instruction immediately */ #define PIO_SM2_PINCTRL_OFFSET (0x10C) /* State machine pin control */ #define PIO_SM3_CLKDIV_OFFSET (0x110) /* Clock divisor register for state machine 3 */ #define PIO_SM3_EXECCTRL_OFFSET (0x114) /* Execution/behavioural settings for state machine 3 */ #define PIO_SM3_SHIFTCTRL_OFFSET (0x118) /* Control behaviour of the input/output shift registers for state machine 3 */ #define PIO_SM3_ADDR_OFFSET (0x11C) /* Current instruction address of state machine 3 */ #define PIO_SM3_INSTR_OFFSET (0x120) /* Instruction currently addressed by state machine or execute an instruction immediately */ #define PIO_SM3_PINCTRL_OFFSET (0x124) /* State machine pin control */ #define PIO_INTR_OFFSET (0x128) /* Raw Interrupts */ #define PIO_IRQ0_INTE_OFFSET (0x12C) /* Interrupt Enable for irq0 */ #define PIO_IRQ0_INTF_OFFSET (0x130) /* Interrupt Force for irq0 */ #define PIO_IRQ0_INTS_OFFSET (0x134) /* Interrupt status after masking & forcing for irq0 */ #define PIO_IRQ1_INTE_OFFSET (0x138) /* Interrupt Enable for irq1 */ #define PIO_IRQ1_INTF_OFFSET (0x13C) /* Interrupt Force for irq1 */ #define PIO_IRQ1_INTS_OFFSET (0x140) /* Interrupt status after masking & forcing for irq1 */ /* PIO_CTRL_OFFSET @0x000*/ #define PIO_SM_ENABLE_POS (0U) #define PIO_SM_ENABLE_MASK (0xF << PIO_SM_ENABLE_POS) #define PIO_SM_RESTART_POS (4U) #define PIO_SM_RESTART_MASK (0xF << PIO_SM_RESTART_POS) #define PIO_CLKDIV_RESTART_POS (8U) #define PIO_CLKDIV_RESTART_MASK (0xF << PIO_CLKDIV_RESTART_POS) /* PIO_FLEVEL_OFFSET @0x00C*/ #define PIO_FLEVEL_TX0_POS (0U) #define PIO_FLEVEL_TX0_MASK (0xF << PIO_FLEVEL_TX0_POS) #define PIO_FLEVEL_RX0_POS (4U) #define PIO_FLEVEL_RX0_MASK (0xF << PIO_FLEVEL_RX0_POS) #define PIO_FLEVEL_TX1_POS (8U) #define PIO_FLEVEL_TX1_MASK (0xF << PIO_FLEVEL_TX1_POS) #define PIO_FLEVEL_RX1_POS (12U) #define PIO_FLEVEL_RX1_MASK (0xF << PIO_FLEVEL_RX1_POS) #define PIO_FLEVEL_TX2_POS (16U) #define PIO_FLEVEL_TX2_MASK (0xF << PIO_FLEVEL_TX2_POS) #define PIO_FLEVEL_RX2_POS (20U) #define PIO_FLEVEL_RX2_MASK (0xF << PIO_FLEVEL_RX2_POS) #define PIO_FLEVEL_TX3_POS (24U) #define PIO_FLEVEL_TX3_MASK (0xF << PIO_FLEVEL_TX3_POS) #define PIO_FLEVEL_RX3_POS (28U) #define PIO_FLEVEL_RX3_MASK (0xF << PIO_FLEVEL_RX3_POS) /* PIO_SM0/1/2/3_CLKDIV_OFFSET @0x0C8/0x0E0/0x0F8/0x110 */ #define PIO_CLKDIV_FRAC_POS (8U) #define PIO_CLKDIV_FRAC_MASK (0xFF << PIO_CLKDIV_FRAC_POS) #define PIO_CLKDIV_INT_POS (16U) #define PIO_CLKDIV_INT_MASK (0xFFFF << PIO_CLKDIV_INT_POS) /* PIO_SM0/1/2/3_EXECCTRL_OFFSET @0x0CC/0x0E4/0x0FC/0x114 */ #define PIO_STATUS_N_POS (0U) #define PIO_STATUS_N_MASK (0xF << PIO_STATUS_N_POS) #define PIO_STATUS_SEL (1 << 4U) #define PIO_WRAP_BOTTOM_POS (7U) #define PIO_WRAP_BOTTOM_MASK (0x1F << PIO_WRAP_BOTTOM_POS) #define PIO_WRAP_TOP_POS (12U) #define PIO_WRAP_TOP_MASK (0x1F << PIO_WRAP_TOP_POS) #define PIO_OUT_STICKY (1 << 17U) #define PIO_INLINE_OUT_EN (1 << 18U) #define PIO_OUT_EN_SEL_POS (19U) #define PIO_OUT_EN_SEL_MASK (0x1F << PIO_OUT_EN_SEL_POS) #define PIO_JMP_PIN_POS (24U) #define PIO_JMP_PIN_MASK (0x1F << PIO_JMP_PIN_POS) #define PIO_SIDE_PINDIR (1 << 29U) #define PIO_SIDE_EN (1 << 30U) #define PIO_EXEC_STALLED (1 << 31U) /* PIO_SM0/1/2/3_SHIFTCTRL_OFFSET @0x0D0/0x0E8/0x100/0x118 */ #define PIO_AUTOPUSH (1 << 16U) #define PIO_AUTOPULL (1 << 17U) #define PIO_IN_SHIFTDIR (1 << 18U) #define PIO_OUT_SHIFTDIR (1 << 19U) #define PIO_PUSH_THRESH_POS (20U) #define PIO_PUSH_THRESH_MASK (0x1F << PIO_PUSH_THRESH_POS) #define PIO_PULL_THRESH_POS (25U) #define PIO_PULL_THRESH_MASK (0x1F << PIO_PULL_THRESH_POS) #define PIO_FJOIN_TX (1 << 30U) #define PIO_FJOIN_RX (1 << 31U) /* PIO_SM0/1/2/3_ADDR_OFFSET @0x0D4/0x0EC/0x104/0x11C */ #define PIO_ADDR_POS (0U) #define PIO_ADDR_MASK (0x1F << PIO_ADDR_POS) /* PIO_SM0/1/2/3_INSTR_OFFSET @0x0D8/0x0F0/0x108/0x120 */ #define PIO_INSTR_POS (0U) #define PIO_INSTR_MASK (0xFFFF << PIO_INSTR_POS) /* PIO_SM0/1/2/3_PINCTRL_OFFSET @0x0DC/0x0F4/0x10C/0x124 */ #define PIO_OUT_BASE_POS (0U) #define PIO_OUT_BASE_MASK (0x1F << PIO_OUT_BASE_POS) #define PIO_SET_BASE_POS (5U) #define PIO_SET_BASE_MASK (0x1F << PIO_SET_BASE_POS) #define PIO_SIDESET_BASE_POS (10U) #define PIO_SIDESET_BASE_MASK (0x1F << PIO_SIDESET_BASE_POS) #define PIO_IN_BASE_POS (15U) #define PIO_IN_BASE_MASK (0x1F << PIO_IN_BASE_POS) #define PIO_OUT_COUNT_POS (20U) #define PIO_OUT_COUNT_MASK (0x3F << PIO_OUT_COUNT_POS) #define PIO_SET_COUNT_POS (26U) #define PIO_SET_COUNT_MASK (0x7 << PIO_SET_COUNT_POS) #define PIO_SIDESET_COUNT_POS (29U) #define PIO_SIDESET_COUNT_MASK (0x7 << PIO_SIDESET_COUNT_POS) #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } #endif #endif /* __HARDWARE_PIO_REG_H__ */