71 lines
2.5 KiB
C
71 lines
2.5 KiB
C
/*************************************************************************//**
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* @file system_RP2040.c
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* @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
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* Device RP2040
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* @version V1.0.0
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* @date 5. May 2021
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*****************************************************************************/
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/*
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* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include "RP2040.h"
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#include "system.h"
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#include "clock.h"
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/*---------------------------------------------------------------------------
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System Core Clock Variable
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*---------------------------------------------------------------------------*/
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#define MacroSystemCoreClock (200 * 1000 * 1000)
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uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/
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volatile uint32_t tick_1ms;
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/*---------------------------------------------------------------------------
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System Core Clock function
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*---------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void)
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{
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SystemCoreClock = MacroSystemCoreClock;
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}
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/*---------------------------------------------------------------------------
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System initialization function
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*---------------------------------------------------------------------------*/
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void __attribute__((constructor)) SystemInit (void)
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{
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system_regulator_set(SYSTEM_REGULATOR_VOLTAGE_1P30V);
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clock_ref_set(CLOCK_REF_SRC_XOSC_GLITCHLESS, 1);
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clock_sys_set(CLOCK_SYS_SRC_REF_GLITCHLESS, 1);
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/* refdiv >= 5MHz, VCO=[750:1600]MHz, fbdiv=[16:320], postdiv=[1:7] */
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clock_syspll_init(1, 100, 3, 2); /* 12MHz / 1 * 100 / 3 / 2 = 200MHz */
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clock_sys_set(CLOCK_SYS_SRC_SYSPLL, 1); /* 200MHz / 1 = 200MHz */
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clock_peri_set(ENABLE, CLOCK_PERI_SRC_SYSPLL);
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SystemCoreClockUpdate();
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/* 1ms */
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SysTick_Config(MacroSystemCoreClock / 1000);
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}
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void isr_systick(void)
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{
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tick_1ms++;
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} |