204 lines
6.1 KiB
C
204 lines
6.1 KiB
C
#ifndef __HARDWARE_CLOCK_REG_H__
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#define __HARDWARE_CLOCK_REG_H__
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/* ROSC_BASE @0x40060000 */
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#define CLOCK_ROSC_CTRL_OFFSET (0x000)
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#define CLOCK_ROSC_FREQA_OFFSET (0x004)
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#define CLOCK_ROSC_FREQB_OFFSET (0x008)
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#define CLOCK_ROSC_DORMANT_OFFSET (0x00C)
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#define CLOCK_ROSC_DIV_OFFSET (0x010)
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#define CLOCK_ROSC_PHASE_OFFSET (0x014)
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#define CLOCK_ROSC_STATUS_OFFSET (0x018)
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#define CLOCK_ROSC_RANDOMBIT_OFFSET (0x01C)
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#define CLOCK_ROSC_COUNT_OFFSET (0x020)
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/* XOSC_BASE @0x40024000 */
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#define CLOCK_XOSC_CTRL_OFFSET (0x000)
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#define CLOCK_XOSC_STATUS_OFFSET (0x004)
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#define CLOCK_XOSC_DORMANT_OFFSET (0x008)
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#define CLOCK_XOSC_STARTUP_OFFSET (0x00C)
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#define CLOCK_XOSC_COUNT_OFFSET (0x01C)
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/* PLL_SYS_BASE @0x40028000 */
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/* PLL_USB_BASE @0x4002C000 */
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#define CLOCK_PLL_CS_OFFSET (0x000)
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#define CLOCK_PLL_PWR_OFFSET (0x004)
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#define CLOCK_PLL_FBDIV_INT_OFFSET (0x008)
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#define CLOCK_PLL_PRIM_OFFSET (0x00C)
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/* CLOCKS_BASE @0x40008000 */
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#define CLOCK_CTRL_OFFSET (0x000)
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#define CLOCK_DIV_OFFSET (0x004)
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#define CLOCK_SELECTED_OFFSET (0x008)
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#define CLOCK_GPOUT0_CTRL_OFFSET (0x000)
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#define CLOCK_GPOUT0_DIV_OFFSET (0x004)
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#define CLOCK_GPOUT0_SELECTED_OFFSET (0x008)
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#define CLOCK_GPOUT1_CTRL_OFFSET (0x00C)
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#define CLOCK_GPOUT1_DIV_OFFSET (0x010)
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#define CLOCK_GPOUT1_SELECTED_OFFSET (0x014)
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#define CLOCK_GPOUT2_CTRL_OFFSET (0x018)
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#define CLOCK_GPOUT2_DIV_OFFSET (0x01C)
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#define CLOCK_GPOUT2_SELECTED_OFFSET (0x020)
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#define CLOCK_GPOUT3_CTRL_OFFSET (0x024)
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#define CLOCK_GPOUT3_DIV_OFFSET (0x028)
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#define CLOCK_GPOUT3_SELECTED_OFFSET (0x02C)
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#define CLOCK_REF_CTRL_OFFSET (0x030)
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#define CLOCK_REF_DIV_OFFSET (0x034)
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#define CLOCK_REF_SELECTED_OFFSET (0x038)
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#define CLOCK_SYS_CTRL_OFFSET (0x03C)
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#define CLOCK_SYS_DIV_OFFSET (0x040)
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#define CLOCK_SYS_SELECTED_OFFSET (0x044)
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#define CLOCK_PERI_CTRL_OFFSET (0x048)
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#define CLOCK_PERI_DIV_OFFSET (0x04C)
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#define CLOCK_PERI_SELECTED_OFFSET (0x050)
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#define CLOCK_USB_CTRL_OFFSET (0x054)
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#define CLOCK_USB_DIV_OFFSET (0x058)
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#define CLOCK_USB_SELECTED_OFFSET (0x05C)
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#define CLOCK_ADC_CTRL_OFFSET (0x060)
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#define CLOCK_ADC_DIV_OFFSET (0x064)
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#define CLOCK_ADC_SELECTED_OFFSET (0x068)
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#define CLOCK_RTC_CTRL_OFFSET (0x06C)
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#define CLOCK_RTC_DIV_OFFSET (0x070)
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#define CLOCK_RTC_SELECTED_OFFSET (0x074)
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/* CLOCK_ROSC_CTRL_OFFSET */
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#define CLOCK_ROSC_FREQ_RANGE_POS (0)
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#define CLOCK_ROSC_FREQ_RANGE_MASK (0xFFF)
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#define CLOCK_ROSC_ENABLE_POS (12)
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#define CLOCK_ROSC_ENABLE_MASK (0xFFF)
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/* CLOCK_ROSC_FREQ_OFFSET */
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#define CLOCK_ROSC_STRENGTH_MASK (0x7)
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/* CLOCK_XOSC_CTRL_OFFSET */
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#define CLOCK_XOSC_FREQ_RANGE_POS (0)
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#define CLOCK_XOSC_FREQ_RANGE_MASK (0xFFF)
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#define CLOCK_XOSC_ENABLE_POS (12)
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#define CLOCK_XOSC_ENABLE_MASK (0xFFF)
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/* CLOCK_XOSC_STARTUP_OFFSET */
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#define CLOCK_XOSC_STARTUP_DELAY_POS (0)
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#define CLOCK_XOSC_STARTUP_DELAY_MASK (0x3FFF)
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#define CLOCK_XOSC_STARTUP_X4_POS (20)
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/* CLOCK_PLL_CS_OFFSET @ 0x000 */
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#define CLOCK_PLL_CS_REFDIV_POS (0)
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#define CLOCK_PLL_CS_REFDIV_MASK (0x3F << CLOCK_PLL_CS_REFDIV_POS)
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#define CLOCK_PLL_CS_BYPASS (1 << 8U)
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#define CLOCK_PLL_CS_LOCK (1 << 31U)
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/* CLOCK_PLL_PWR_OFFSET @ 0x004 */
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#define CLOCK_PLL_PWR_PD (1 << 0U)
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#define CLOCK_PLL_PWR_DSMPD (1 << 2U)
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#define CLOCK_PLL_PWR_POSTDIVPD (1 << 3U)
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#define CLOCK_PLL_PWR_VCOPD (1 << 5U)
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/* CLOCK_PLL_PRIM_OFFSET @ 0x00C */
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#define CLOCK_PLL_PRIM_POSTDIV2_POS (12U)
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#define CLOCK_PLL_PRIM_POSTDIV2_MASK (0x7 << CLOCK_PLL_PRIM_POSTDIV2_POS)
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#define CLOCK_PLL_PRIM_POSTDIV1_POS (16U)
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#define CLOCK_PLL_PRIM_POSTDIV1_MASK (0x7 << CLOCK_PLL_PRIM_POSTDIV1_POS)
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/* CLOCK_CTRL_OFFSET @ 0x000 */
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#define CLOCK_CTRL_SRC_POS (0U)
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#define CLOCK_CTRL_AUXSRC_POS (5U)
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#define CLOCK_CTRL_KILL (1 << 10U)
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#define CLOCK_CTRL_ENABLE (1 << 11U)
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#define CLOCK_CTRL_DC50 (1 << 12U)
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#define CLOCK_CTRL_PHASE_POS (16U)
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#define CLOCK_CTRL_NUDGE (1 << 20U)
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/* CLOCK_DIV_OFFSET @0x004 */
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#define CLOCK_DIV_FRAC_POS (0U)
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#define CLOCK_DIV_INT_POS (8U)
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typedef struct {
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io_rw_32 ctrl;
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io_rw_32 div;
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io_rw_32 selected;
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} clock_hw_t;
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typedef struct {
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io_rw_32 ref_khz;
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io_rw_32 min_khz;
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io_rw_32 max_khz;
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io_rw_32 delay;
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io_rw_32 interval;
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io_rw_32 src;
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io_ro_32 status;
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io_ro_32 result;
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} fc_hw_t;
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typedef struct {
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clock_hw_t clk[10];
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struct {
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io_rw_32 ctrl;
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io_rw_32 status;
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} resus;
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fc_hw_t fc0;
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io_rw_32 wake_en0;
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io_rw_32 wake_en1;
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io_rw_32 sleep_en0;
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io_rw_32 sleep_en1;
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io_rw_32 enabled0;
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io_rw_32 enabled1;
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io_rw_32 intr;
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io_rw_32 inte;
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io_rw_32 intf;
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io_rw_32 ints;
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} clocks_hw_t;
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#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
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#define clocks_hw_set ((clocks_hw *const)hw_set_alias_untyped(clocks_hw))
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#define clocks_hw_clear ((clocks_hw *const)hw_clear_alias_untyped(clocks_hw))
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typedef struct {
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io_rw_32 cs;
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io_rw_32 pwr;
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io_rw_32 fbdiv_int;
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io_rw_32 prim;
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} pll_hw_t;
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#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
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#define pll_sys_hw_set ((pll_sys_hw *const)hw_set_alias_untyped(pll_sys_hw))
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#define pll_sys_hw_clear ((pll_sys_hw *const)hw_clear_alias_untyped(pll_sys_hw))
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#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
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#define pll_usb_hw_set ((pll_usb_hw *const)hw_set_alias_untyped(pll_usb_hw))
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#define pll_usb_hw_clear ((pll_usb_hw *const)hw_clear_alias_untyped(pll_usb_hw))
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typedef struct {
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io_rw_32 ctrl;
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io_rw_32 freqa;
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io_rw_32 freqb;
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io_rw_32 dormant;
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io_rw_32 div;
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io_rw_32 phase;
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io_rw_32 status;
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io_rw_32 randombit;
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io_rw_32 count;
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io_rw_32 dftx;
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} rosc_hw_t;
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#define rosc_hw ((rosc_hw_t *const)ROSC_BASE)
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typedef struct {
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io_rw_32 ctrl;
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io_rw_32 status;
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io_rw_32 dormant;
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io_rw_32 startup;
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io_rw_32 _reserved[3];
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io_rw_32 count;
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} xosc_hw_t;
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#define xosc_hw ((xosc_hw_t *const)XOSC_BASE)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HARDWARE_CLOCK_REG_H__ */
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