148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
#include "gpio.h"
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#include "ssi_reg.h"
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#include "flash.h"
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static void flash_cs_force_low(void)
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{
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ioqspi_hw->io[1].ctrl = GPIO_OVER_OUT_LOW;
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}
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static void flash_cs_force_high(void)
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{
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ioqspi_hw->io[1].ctrl = GPIO_OVER_OUT_HIGH;
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}
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static void flash_put_get(uint8_t *tx, uint8_t *rx, uint32_t count, uint32_t rx_skip)
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{
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uint32_t tx_count = count;
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uint32_t rx_count = count;
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while (tx_count || rx_skip || rx_count) {
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uint32_t tx_level = ssi_hw->txflr;
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uint32_t rx_level = ssi_hw->rxflr;
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if (tx_count && tx_level + rx_level < 14) {
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ssi_hw->dr0 = (uint32_t) (tx ? *tx++ : 0);
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--tx_count;
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}
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if (rx_level) {
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uint8_t rxbyte = ssi_hw->dr0;
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if (rx_skip) {
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--rx_skip;
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} else {
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if (rx)
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*rx++ = rxbyte;
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--rx_count;
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}
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}
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}
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flash_cs_force_high();
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}
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static void flash_do_cmd(uint8_t cmd, uint8_t *tx, uint8_t *rx, uint32_t count)
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{
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flash_cs_force_low();
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ssi_hw->dr0 = cmd;
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flash_put_get(tx, rx, count, 1);
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}
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static void flash_put_cmd_addr(uint8_t cmd, uint32_t addr)
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{
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flash_cs_force_low();
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addr |= cmd << 24;
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for (int i = 0; i < 4; ++i) {
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ssi_hw->dr0 = addr >> 24;
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addr <<= 8;
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}
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}
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static void flash_enable_write(void)
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{
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flash_do_cmd(FLASHCMD_WRITE_ENABLE, (void *)0, (void *)0, 0);
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}
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static void flash_wait_ready(void)
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{
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uint8_t stat;
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do {
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flash_do_cmd(FLASHCMD_READ_STATUS, (void *)0, &stat, 1);
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} while (stat & 0x1);
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}
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void flash_erase(uint32_t addr)
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{
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flash_enable_write();
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flash_put_cmd_addr(FLASHCMD_SECTOR_ERASE, addr);
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flash_put_get((void *)0, (void *)0, 0, 4);
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flash_wait_ready();
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}
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void flash_write(uint32_t addr, uint8_t *data, uint32_t length)
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{
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if (length > FLASH_WRITE_SIZE) {
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return;
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}
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flash_enable_write();
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flash_put_cmd_addr(FLASHCMD_PAGE_PROGRAM, addr);
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flash_put_get(data, (void *)0, length, 4);
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flash_wait_ready();
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}
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void flash_read(uint32_t addr, uint8_t *data, uint32_t length)
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{
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flash_put_cmd_addr(FLASHCMD_READ_DATA, addr);
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flash_put_get((void *)0, data, length, 4);
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}
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void flash_enter_quad_xip(uint16_t div)
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{
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uint8_t buffer[8];
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pads_qspi_hw->io_qspi_sclk = (GPIO_DRIVE_8MA >> 32) | (GPIO_SLEW_FAST >> 32);
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hw_clear_bits(&pads_qspi_hw->io_qspi_sd0, GPIO_SCHMITT >> 32);
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hw_clear_bits(&pads_qspi_hw->io_qspi_sd1, GPIO_SCHMITT >> 32);
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hw_clear_bits(&pads_qspi_hw->io_qspi_sd2, GPIO_SCHMITT >> 32);
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hw_clear_bits(&pads_qspi_hw->io_qspi_sd3, GPIO_SCHMITT >> 32);
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ssi_hw->ssienr = 0;
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/* div must be even */
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if (div & 1) {
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div = div + 1;
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}
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ssi_hw->baudr = div;
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ssi_hw->rx_sample_dly = 1;
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/* 8bits per data frame */
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ssi_hw->ctrlr0 = (7 << SSI_CTRLR0_DFS_32_POS) | SSI_CTRLR0_TMOD_VALUE_TX_AND_RX_MASK;
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ssi_hw->ssienr = 1;
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flash_do_cmd(FLASHCMD_READ_STATUS2, (uint8_t *)0, buffer, 1);
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if ((buffer[0] & SREG_DATA) == 0) {
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flash_enable_write();
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buffer[0] = 0;
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buffer[1] = SREG_DATA;
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flash_do_cmd(FLASHCMD_WRITE_STATUS, buffer, (uint8_t *)0, 2);
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flash_wait_ready();
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}
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ssi_hw->ssienr = 0;
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/* 32bits per data frame, quad and xip */
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ssi_hw->ctrlr0 = (31 << SSI_CTRLR0_DFS_32_POS) | \
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SSI_CTRLR0_SPI_FRF_VALUE_QUAD_MASK | \
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SSI_CTRLR0_TMOD_VALUE_EEPROM_READ_MASK;
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/* NDF=0, single 32b read */
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ssi_hw->ctrlr1 = 0;
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ssi_hw->spi_ctrlr0 = (8 << SSI_SPI_CTRLR0_ADDR_L_POS) | \
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(4 << SSI_SPI_CTRLR0_WAIT_CYCLES_POS) | \
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SSI_SPI_CTRLR0_INST_L_VALUE_8B_MASK | \
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SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A_MASK;
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ioqspi_hw->io[1].ctrl = 0;
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ssi_hw->ssienr = 1;
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ssi_hw->dr0 = 0xEB;
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ssi_hw->dr0 = MODE_CONTINUOUS_READ;
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flash_wait_ready();
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ssi_hw->ssienr = 0;
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ssi_hw->spi_ctrlr0 = (MODE_CONTINUOUS_READ << SSI_SPI_CTRLR0_XIP_CMD_POS) | \
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(8 << SSI_SPI_CTRLR0_ADDR_L_POS) | \
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(4 << SSI_SPI_CTRLR0_WAIT_CYCLES_POS) | \
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SSI_SPI_CTRLR0_INST_L_VALUE_NONE_MASK | \
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SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A_MASK;
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ioqspi_hw->io[1].ctrl = 0;
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ssi_hw->ssienr = 1;
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}
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