186 lines
5.5 KiB
C
186 lines
5.5 KiB
C
#ifndef __HARDWARE_DMA_H__
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#define __HARDWARE_DMA_H__
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#include "reg.h"
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#include "dma_reg.h"
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#define DMA_CHANNEL_0 (0)
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#define DMA_CHANNEL_1 (1)
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#define DMA_CHANNEL_2 (2)
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#define DMA_CHANNEL_3 (3)
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#define DMA_CHANNEL_4 (4)
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#define DMA_CHANNEL_5 (5)
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#define DMA_CHANNEL_6 (6)
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#define DMA_CHANNEL_7 (7)
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#define DMA_CHANNEL_8 (8)
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#define DMA_CHANNEL_9 (9)
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#define DMA_CHANNEL_10 (10)
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#define DMA_CHANNEL_11 (11)
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#define DMA_CHANNEL_MAX (12)
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#define DMA_CHANNEL_MASK ((1 << DMA_CHANNEL_MAX) - 1)
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#define DMA_INT_GROUP_0 (0)
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#define DMA_INT_GROUP_1 (1)
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#define DMA_REQ_PIO0_TX0 (0)
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#define DMA_REQ_PIO0_TX1 (1)
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#define DMA_REQ_PIO0_TX2 (2)
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#define DMA_REQ_PIO0_TX3 (3)
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#define DMA_REQ_PIO0_RX0 (4)
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#define DMA_REQ_PIO0_RX1 (5)
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#define DMA_REQ_PIO0_RX2 (6)
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#define DMA_REQ_PIO0_RX3 (7)
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#define DMA_REQ_PIO1_TX0 (8)
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#define DMA_REQ_PIO1_TX1 (9)
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#define DMA_REQ_PIO1_TX2 (10)
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#define DMA_REQ_PIO1_TX3 (11)
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#define DMA_REQ_PIO1_RX0 (12)
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#define DMA_REQ_PIO1_RX1 (13)
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#define DMA_REQ_PIO1_RX2 (14)
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#define DMA_REQ_PIO1_RX3 (15)
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#define DMA_REQ_SPI0_TX (16)
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#define DMA_REQ_SPI0_RX (17)
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#define DMA_REQ_SPI1_TX (18)
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#define DMA_REQ_SPI1_RX (19)
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#define DMA_REQ_UART0_TX (20)
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#define DMA_REQ_UART0_RX (21)
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#define DMA_REQ_UART1_TX (22)
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#define DMA_REQ_UART1_RX (23)
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#define DMA_REQ_PWM_WRAP0 (24)
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#define DMA_REQ_PWM_WRAP1 (25)
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#define DMA_REQ_PWM_WRAP2 (26)
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#define DMA_REQ_PWM_WRAP3 (27)
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#define DMA_REQ_PWM_WRAP4 (28)
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#define DMA_REQ_PWM_WRAP5 (29)
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#define DMA_REQ_PWM_WRAP6 (30)
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#define DMA_REQ_PWM_WRAP7 (31)
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#define DMA_REQ_I2C0_TX (32)
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#define DMA_REQ_I2C0_RX (33)
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#define DMA_REQ_I2C1_TX (34)
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#define DMA_REQ_I2C1_RX (35)
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#define DMA_REQ_ADC (36)
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#define DMA_REQ_XIP_STREAM (37)
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#define DMA_REQ_XIP_SSITX (38)
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#define DMA_REQ_XIP_SSIRX (39)
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#define DMA_REQ_TIMER_0 (0x3B)
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#define DMA_REQ_TIMER_1 (0x3C)
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#define DMA_REQ_TIMER_2 (0x3D)
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#define DMA_REQ_TIMER_3 (0x3E)
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#define DMA_REQ_FOREVER (0x3F)
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#define DMA_DATA_SIZE_8BIT (0)
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#define DMA_DATA_SIZE_16BIT (1)
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#define DMA_DATA_SIZE_32BIT (2)
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#define DMA_RING_SIZE_NONE (0)
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#define DMA_RING_SIZE_2B (1)
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#define DMA_RING_SIZE_4B (2)
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#define DMA_RING_SIZE_8B (3)
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#define DMA_RING_SIZE_16B (4)
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#define DMA_RING_SIZE_32B (5)
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#define DMA_RING_SIZE_64B (6)
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#define DMA_RING_SIZE_128B (7)
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#define DMA_RING_SIZE_256B (8)
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#define DMA_RING_SIZE_512B (9)
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#define DMA_RING_SIZE_1kB (10)
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#define DMA_RING_SIZE_2kB (11)
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#define DMA_RING_SIZE_4kB (12)
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#define DMA_RING_SIZE_8kB (13)
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#define DMA_RING_SIZE_16kB (14)
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#define DMA_RING_SIZE_32kB (15)
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#define DMA_SNIFF_CALC_CRC32 (0)
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#define DMA_SNIFF_CALC_CRC32_BITREV (1)
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#define DMA_SNIFF_CALC_CRC16_CCITT (2)
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#define DMA_SNIFF_CALC_CRC16_CCITT_BITREV (3)
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#define DMA_SNIFF_CALC_EVEN_CHECKSUM (14)
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#define DMA_SNIFF_CALC_SUM32 (15)
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union dma_ctrl_s {
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struct {
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uint32_t en : 1; /* [ 0], r/w */
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uint32_t high_priority : 1; /* [ 1], r/w */
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uint32_t data_size : 2; /* [ 3: 2], r/w */
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uint32_t incr_read : 1; /* [ 4], r/w */
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uint32_t incr_write : 1; /* [ 5], r/w */
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uint32_t ring_size : 4; /* [ 9: 6], r/w */
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uint32_t ring_sel_write : 1; /* [ 10], r/w */
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uint32_t chain_to : 4; /* [14:11], r/w */
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uint32_t request : 6; /* [20:15], r/w */
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uint32_t irq_quiet : 1; /* [ 21], r/w */
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uint32_t byte_swap : 1; /* [ 22], r/w */
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uint32_t sniff_en : 1; /* [ 23], r/w */
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uint32_t busy : 1; /* [ 24], ro */
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uint32_t reserved : 4; /* [28:25], reserved */
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uint32_t error_write : 1; /* [ 29], wc */
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uint32_t error_read : 1; /* [ 30], wc */
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uint32_t error_ahb : 1; /* [ 31], ro */
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} bits;
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uint32_t word;
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};
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struct dma_cfg_s {
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uint32_t read_addr;
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uint32_t write_addr;
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uint32_t trans_count;
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// union dma_ctrl_s ctrl;
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uint8_t channel;
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uint8_t request;
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uint8_t data_size;
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uint8_t incr_read;
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uint8_t incr_write;
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uint8_t irq_quiet;
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uint8_t byte_swap;
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uint8_t chain_to;
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uint8_t high_priority;
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uint8_t ring_sel_write;
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uint8_t ring_size;
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uint8_t sniff_en;
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};
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struct dma_sniff_cfg_s {
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uint8_t channel;
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uint8_t calc;
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uint8_t byte_swap;
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uint8_t out_rev; /* bit = ~bit */
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uint8_t out_inv; /* bit31-0 -> bit0-31 */
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dma_init(struct dma_cfg_s *cfg);
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void dma_enable_and_trig(uint8_t ch);
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void dma_disable(uint8_t ch);
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void dma_trig_multi(uint16_t chs);
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void dma_abort_multi(uint16_t chs);
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void dma_read_addr_update(uint8_t ch, uint32_t addr);
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void dma_write_addr_update(uint8_t ch, uint32_t addr);
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void dma_trans_count_update(uint8_t ch, uint8_t count);
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uint32_t dma_trans_count_remain_get(uint8_t ch);
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void dma_timer_set(uint8_t ch, uint16_t x, uint16_t y);
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void dma_sniff_init(struct dma_sniff_cfg_s *cfg);
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void dma_sniff_enable(void);
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void dma_sniff_disable(void);
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void dma_sniff_write(uint32_t seed);
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uint32_t dma_sniff_read(void);
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uint32_t dma_int_get_raw_status(void);
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void dma_int_clear_raw_status(uint32_t chs);
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uint32_t dma_int_get_status(uint8_t int_group);
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void dma_int_clear(uint8_t group, uint32_t chs);
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void dma_int_enable(uint8_t int_group, uint32_t chs);
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void dma_int_disable(uint8_t int_group, uint32_t chs);
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void dma_int_force(uint8_t int_group, uint32_t chs);
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void dma_int_deforce(uint8_t int_group, uint32_t chs);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HARDWARE_DMA_H__ */
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