106 lines
3.8 KiB
C
106 lines
3.8 KiB
C
#ifndef __QSPI_FLASH_H__
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#define __QSPI_FLASH_H__
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#include "stm32h7xx_hal.h"
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/* Definition for QSPI clock resources */
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#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
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#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
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#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_BK1_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
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#define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define QSPI_MDMA_CLK_ENABLE() __HAL_RCC_MDMA_CLK_ENABLE()
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#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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/* Definition for QSPI Pins */
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#define QSPI_CLK_PIN GPIO_PIN_2
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#define QSPI_CLK_GPIO_PORT GPIOB
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/* Bank 1 */
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#define QSPI_BK1_CS_PIN GPIO_PIN_6
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#define QSPI_BK1_CS_GPIO_PORT GPIOB
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#define QSPI_BK1_D0_PIN GPIO_PIN_11
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#define QSPI_BK1_D0_GPIO_PORT GPIOD
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#define QSPI_BK1_D1_PIN GPIO_PIN_12
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#define QSPI_BK1_D1_GPIO_PORT GPIOD
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#define QSPI_BK1_D2_PIN GPIO_PIN_2
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#define QSPI_BK1_D2_GPIO_PORT GPIOE
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#define QSPI_BK1_D3_PIN GPIO_PIN_13
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#define QSPI_BK1_D3_GPIO_PORT GPIOD
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/* W25Q64JV memory */
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/* Size of the flash */
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#define QSPI_FLASH_SIZE 22
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#define QSPI_PAGE_SIZE 256
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/* Reset Operations */
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#define RESET_ENABLE_CMD 0x66
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#define RESET_MEMORY_CMD 0x99
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/* Identification Operations */
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#define READ_ID_CMD 0x9F
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#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
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/* Read Operations */
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#define READ_CMD 0x03
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#define FAST_READ_CMD 0x0B
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#define DUAL_OUT_FAST_READ_CMD 0x3B
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#define DUAL_INOUT_FAST_READ_CMD 0xBB
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#define QUAD_OUT_FAST_READ_CMD 0x6B
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#define QUAD_INOUT_FAST_READ_CMD 0xEB
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/* Write Operations */
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#define WRITE_ENABLE_CMD 0x06
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#define WRITE_DISABLE_CMD 0x04
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/* Register Operations */
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#define READ_STATUS_REG_CMD 0x05
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#define WRITE_STATUS_REG_CMD 0x01
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/* Program Operations */
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#define PAGE_PROG_CMD 0x02
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#define QUAD_IN_FAST_PROG_CMD 0x32
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/* Erase Operations */
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#define SECTOR_ERASE_CMD 0x20 /* 4K-bytes */
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#define SUBBLOCK_ERASE_CMD 0x52 /* 32K-bytes */
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#define BLOCK_ERASE_CMD 0xD8 /* 64K-bytes */
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#define CHIP_ERASE_CMD 0xC7
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#define PROG_ERASE_RESUME_CMD 0x7A
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#define PROG_ERASE_SUSPEND_CMD 0x75
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/* Quad Operations */
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#define ENTER_QUAD_CMD 0x38
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#define EXIT_QUAD_CMD 0xFF
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/* Default dummy clocks cycles */
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#define DUMMY_CLOCK_CYCLES_READ 8
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#define DUMMY_CLOCK_CYCLES_READ_QUAD 8
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/* End address of the QSPI memory */
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#define QSPI_END_ADDR (1 << (QSPI_FLASH_SIZE + 1))
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#ifdef __cplusplus
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extern "C" {
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#endif
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void qspi_flash_init(uint32_t div);
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void qspi_flash_deinit(void);
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uint32_t qspi_flash_write(uint32_t addr, uint8_t *data, uint32_t length);
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uint32_t qspi_flash_read(uint32_t addr, uint8_t *data, uint32_t length);
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uint32_t qspi_flash_erase_4kbytes(uint32_t addr);
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uint32_t qspi_flash_erase_32kbytes(uint32_t addr);
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uint32_t qspi_flash_erase_64kbytes(uint32_t addr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __QSPI_FLASH_H__ */
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